Fixes to various config files.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/arch/i386/Config.lb

@@ -1,4 +1,3 @@
-default ARCH=i386
 dir lib
 dir boot
 dir smp

src/arch/i386/boot/Config.lb

@@ -1,3 +1,5 @@
+uses HAVE_PIRQ_TABLE
+
 object boot.o
 object linuxbios_table.o
 object tables.o

src/arch/i386/smp/Config.lb

@@ -1,3 +1,6 @@
+uses HAVE_MP_TABLE
+uses CONFIG_SMP
+
 if HAVE_MP_TABLE
   object mpspec.o 
 end

src/config/Options.lb

@@ -371,7 +371,7 @@ end
 ###############################################
 
 define CONFIG_SMP
-	default none
+	default 0
 	export always
 	comment "Define if we support SMP"
 end

src/cpu/k7/Config.lb

@@ -1,3 +1,3 @@
-option k7=1
-default  CPU_FIXUP=1
+uses k7
+uses CPU_FIXUP
 #object cpufixup.o

src/cpu/k8/Config.lb

@@ -1,3 +1,4 @@
-default k8=1
-default  CPU_FIXUP=1
-object cpufixup.o
+uses CPU_FIXUP
+if CPU_FIXUP
+  object cpufixup.o
+end

src/cpu/p5/Config.lb

@@ -1,5 +1,5 @@
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
-option i586=1
+uses  CONFIG_UDELAY_TSC
+
 object cpuid.o
 if CONFIG_UDELAY_TSC object delay_tsc.o  end
 #object tsc.o

src/cpu/p6/Config.lb

@@ -1,5 +1,5 @@
-option i686=1
-option INTEL_PPRO_MTRR=1
+uses i686
+uses INTEL_PPRO_MTRR
 #object microcode.o
 object mtrr.o
 #object l2_cache.o

targets/arima/hdama/Config.lb

@@ -10,14 +10,19 @@ uses CONFIG_COMPRESS
 uses CONFIG_IOAPIC
 uses CONFIG_ROM_STREAM
 uses CONFIG_ROM_STREAM_START
+uses CONFIG_UDELAY_TSC
+uses CPU_FIXUP
 uses ENABLE_FIXED_AND_VARIABLE_MTRRS
 uses FALLBACK_SIZE
 uses FINAL_MAINBOARD_FIXUP
 uses HAVE_FALLBACK_BOOT
 uses HAVE_MP_TABLE
 uses HAVE_PIRQ_TABLE
+uses i686
+uses INTEL_PPRO_MTRR
 uses HEAP_SIZE
 uses IRQ_SLOT_COUNT
+uses k7
 uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAX_CPUS
@@ -37,6 +42,13 @@ uses USE_FALLBACK_IMAGE
 uses USE_OPTION_TABLE
 
 option HAVE_MP_TABLE=0
+option CPU_FIXUP=1
+option CONFIG_UDELAY_TSC=0
+option i686=1
+option INTEL_PPRO_MTRR=1
+option k7=1
+
+
 ### Customize our winbond superio chip for this motherboard
 ###
 option SIO_BASE=0x2e