cpu/intel/smm: Drop em64t save state
This save state is just plainly wrong in many regards and em64t100 should be used. Checked with a model 0x17 core2 CPU. Change-Id: I4d89691e87c91dd12b34a44b74849b18b4ac5369 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -18,7 +18,6 @@
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#include <cpu/x86/smm.h>
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#include <cpu/x86/smi_deprecated.h>
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#include <cpu/amd/amd64_save_state.h>
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#include <cpu/intel/em64t_save_state.h>
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#include <cpu/intel/em64t100_save_state.h>
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#include <cpu/intel/em64t101_save_state.h>
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#include <cpu/x86/legacy_save_state.h>
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@ -29,7 +28,7 @@
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typedef enum {
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AMD64,
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EM64T,
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EM64T100,
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EM64T101,
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LEGACY
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} save_state_type_t;
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@ -38,7 +37,7 @@ typedef struct {
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save_state_type_t type;
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union {
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amd64_smm_state_save_area_t *amd64_state_save;
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em64t_smm_state_save_area_t *em64t_state_save;
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em64t100_smm_state_save_area_t *em64t100_state_save;
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em64t101_smm_state_save_area_t *em64t101_state_save;
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legacy_smm_state_save_area_t *legacy_state_save;
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};
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@ -178,10 +177,10 @@ void smi_handler(u32 smm_revision)
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SMM_LEGACY_ARCH_OFFSET, node);
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break;
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case 0x00030100:
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state_save.type = EM64T;
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state_save.em64t_state_save =
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state_save.type = EM64T100;
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state_save.em64t100_state_save =
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smm_save_state(smm_base,
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SMM_EM64T_ARCH_OFFSET, node);
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SMM_EM64T100_ARCH_OFFSET, node);
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break;
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case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */
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state_save.type = EM64T101;
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@ -17,10 +17,8 @@
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#include <types.h>
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#include <cpu/x86/smm.h>
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/* Intel Revision 30100 SMM State-Save Area
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* The following processor architectures use this:
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* - Bay Trail
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*/
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/* Intel Revision 30100 SMM State-Save Area */
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#define SMM_EM64T100_ARCH_OFFSET 0x7c00
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#define SMM_EM64T100_SAVE_STATE_OFFSET \
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SMM_SAVE_STATE_BEGIN(SMM_EM64T100_ARCH_OFFSET)
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@ -1,101 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __EM64T_SAVE_STATE_H__
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#define __EM64T_SAVE_STATE_H__
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#include <types.h>
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#include <cpu/x86/smm.h>
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/* Intel Core 2 (EM64T) SMM State-Save Area
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* starts @ 0x7c00
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*/
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#define SMM_EM64T_ARCH_OFFSET 0x7c00
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#define SMM_EM64T_SAVE_STATE_OFFSET \
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SMM_SAVE_STATE_BEGIN(SMM_EM64T_ARCH_OFFSET)
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typedef struct {
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u8 reserved0[256];
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u8 reserved1[208];
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u32 gdtr_upper_base;
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u32 ldtr_upper_base;
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u32 idtr_upper_base;
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u8 reserved2[4];
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u64 io_rdi;
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u64 io_rip;
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u64 io_rcx;
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u64 io_rsi;
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u64 cr4;
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u8 reserved3[68];
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u64 gdtr_base;
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u64 idtr_base;
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u64 ldtr_base;
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u8 reserved4[84];
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u32 smm_revision;
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u32 smbase;
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u16 io_restart;
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u16 autohalt_restart;
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u8 reserved5[24];
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u64 r15;
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u64 r14;
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u64 r13;
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u64 r12;
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u64 r11;
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u64 r10;
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u64 r9;
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u64 r8;
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u64 rax;
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u64 rcx;
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u64 rdx;
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u64 rbx;
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u64 rsp;
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u64 rbp;
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u64 rsi;
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u64 rdi;
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u64 io_mem_addr;
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u32 io_misc_info;
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u32 es_sel;
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u32 cs_sel;
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u32 ss_sel;
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u32 ds_sel;
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u32 fs_sel;
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u32 gs_sel;
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u32 ldtr_sel;
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u32 tr_sel;
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u64 dr7;
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u64 dr6;
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u64 rip;
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u64 efer;
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u64 rflags;
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u64 cr3;
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u64 cr0;
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} __packed em64t_smm_state_save_area_t;
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#endif
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