new intel io hub.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
c66444c175
commit
182615d635
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config i82801dbm.h
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driver i82801dbm.o
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driver i82801dbm_usb.o
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driver i82801dbm_lpc.o
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driver i82801dbm_ide.o
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driver i82801dbm_sata.o
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driver i82801dbm_usb2.o
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driver i82801dbm_ac97.o
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#driver i82801dbm_nic.o
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#driver i82801dbm_pci.o
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object i82801dbm_reset.o
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@ -0,0 +1,16 @@
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//kind of cmos_err for ich5
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#define RTC_FAILED (1 <<2)
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#define GEN_PMCON_3 0xa4
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static void check_cmos_failed(void)
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{
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uint8_t byte;
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byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
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if( byte & RTC_FAILED){
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//clear bit 1 and bit 2
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byte = cmos_read(RTC_BOOT_BYTE);
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byte &= 0x0c;
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byte |= MAX_REBOOT_CNT << 4;
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cmos_write(byte, RTC_BOOT_BYTE);
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}
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}
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/chip.h>
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#include "i82801dbm.h"
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void i82801dbm_enable(device_t dev)
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{
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device_t lpc_dev;
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unsigned int index;
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uint16_t reg_old, reg;
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// all 82801dbm device ares in bus 0
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unsigned int devfn;
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devfn = PCI_DEVFN(0x1f, 0); // lpc
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lpc_dev = dev_find_slot(0, devfn); // 0
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if (!lpc_dev ) {
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return;
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}
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#if 0
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if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) ||
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(lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_1F0)) {
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uint32_t id;
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id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
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if (id != (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_82801ER_1F0 << 16))) {
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return;
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}
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}
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#endif
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index = (dev->path.u.pci.devfn & 7);
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if((dev->path.u.pci.devfn & ~0x7)==devfn) { // D=0x1f
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if(index==0){ //1f0
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index = 14;
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}
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} else { // D=0x1d
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index += 8;
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}
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reg_old = pci_read_config16(lpc_dev, FUNC_DIS);
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reg = reg_old;
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reg &= ~(1<<index); // enable it
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if (!dev->enabled) {
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reg |= (1<<index); // disable it
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}
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if (reg != reg_old) {
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pci_write_config16(lpc_dev, FUNC_DIS, reg);
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}
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reg = pci_read_config16(lpc_dev, FUNC_DIS);
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}
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struct chip_control southbridge_intel_i82801dbm_control = {
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.name = "Intel 82801dbm Southbridge",
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.enable_dev = i82801dbm_enable,
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};
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@ -0,0 +1,81 @@
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#ifndef I82801ER_H
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#define I82801ER_H
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struct southbridge_intel_i82801er_config
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{
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};
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struct chip_control;
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extern struct chip_control southbridge_intel_i82801er_control;
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extern void i82801er_enable(device_t dev);
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/*
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000 = Non-combined. P0 is primary master. P1 is secondary master.
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001 = Non-combined. P0 is secondary master. P1 is primary master.
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100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; Primary IDE channel
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disabled.
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101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.
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110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary slave; Secondary IDE
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channel disabled.
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111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.
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*/
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#define ICH5_SATA_ADDRESS_MAP 0
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#define PCI_DMA_CFG 0x90
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#define SERIRQ_CNTL 0x64
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#define GEN_CNTL 0xd0
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#define GEN_STS 0xd4
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#define RTC_CONF 0xd8
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#define GEN_PMCON_3 0xa4
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#define PCICMD 0x04
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#define PMBASE 0x40
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#define ACPI_CNTL 0x44
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#define BIOS_CNTL 0x4E
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#define GPIO_BASE 0x58
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#define GPIO_CNTL 0x5C
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#define PIRQA_ROUT 0x60
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#define PIRQE_ROUT 0x68
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#define COM_DEC 0xE0
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#define LPC_EN 0xE6
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#define FUNC_DIS 0xF2
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/* 1e f0 244e */
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#define CMD 0x04
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#define SBUS_NUM 0x19
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#define SUB_BUS_NUM 0x1A
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#define SMLT 0x1B
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#define IOBASE 0x1C
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#define IOLIM 0x1D
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#define MEMBASE 0x20
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#define MEMLIM 0x22
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#define CNF 0x50
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#define MTT 0x70
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#define PCI_MAST_STS 0x82
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#define RTC_FAILED (1 <<2)
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#define SMBUS_IO_BASE 0x1000
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#define SMBHSTSTAT 0x0
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#define SMBHSTCTL 0x2
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#define SMBHSTCMD 0x3
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#define SMBXMITADD 0x4
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#define SMBHSTDAT0 0x5
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#define SMBHSTDAT1 0x6
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#define SMBBLKDAT 0x7
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#define SMBTRNSADD 0x9
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#define SMBSLVDATA 0xa
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#define SMLINK_PIN_CTL 0xe
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#define SMBUS_PIN_CTL 0xf
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/* Between 1-10 seconds, We should never timeout normally
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* Longer than this is just painful when a timeout condition occurs.
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*/
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#define SMBUS_TIMEOUT (100*1000)
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#endif /* I82801ER_H */
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/*
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* (C) 2003 Linux Networx
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "i82801dbm.h"
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static struct device_operations ac97audio_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.enable = i82801dbm_enable,
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.init = 0,
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.scan_bus = 0,
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};
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static struct pci_driver ac97audio_driver __pci_driver = {
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.ops = &ac97audio_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801ER_1F5,
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};
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static struct device_operations ac97modem_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.enable = i82801dbm_enable,
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.init = 0,
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.scan_bus = 0,
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};
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static struct pci_driver ac97modem_driver __pci_driver = {
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.ops = &ac97modem_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801ER_1F6,
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};
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//#define SMBUS_IO_BASE 0x1000
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#define SMBUS_IO_BASE 0x0f00
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#define SMBHSTSTAT 0x0
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#define SMBHSTCTL 0x2
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#define SMBHSTCMD 0x3
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#define SMBXMITADD 0x4
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#define SMBHSTDAT0 0x5
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#define SMBHSTDAT1 0x6
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#define SMBBLKDAT 0x7
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#define SMBTRNSADD 0x9
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#define SMBSLVDATA 0xa
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#define SMLINK_PIN_CTL 0xe
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#define SMBUS_PIN_CTL 0xf
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/* Between 1-10 seconds, We should never timeout normally
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* Longer than this is just painful when a timeout condition occurs.
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*/
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#define SMBUS_TIMEOUT (100*1000*10)
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static void enable_smbus(void)
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{
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device_t dev;
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dev = pci_locate_device(PCI_ID(0x8086, 0x24d3), 0);
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if (dev == PCI_DEV_INVALID) {
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die("SMBUS controller not found\r\n");
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}
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print_debug("SMBus controller enabled\r\n");
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/* set smbus iobase */
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pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
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/* Set smbus enable */
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pci_write_config8(dev, 0x40, 0x01);
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/* Set smbus iospace enable */
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pci_write_config16(dev, 0x4, 0x01);
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/* Disable interrupt generation */
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outb(0, SMBUS_IO_BASE + SMBHSTCTL);
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/* clear any lingering errors, so the transaction will run */
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outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
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}
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static inline void smbus_delay(void)
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{
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outb(0x80, 0x80);
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}
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static int smbus_wait_until_ready(void)
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{
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned char val;
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smbus_delay();
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val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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if ((val & 1) == 0) {
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break;
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}
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if(loops == (SMBUS_TIMEOUT / 2)) {
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outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
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SMBUS_IO_BASE + SMBHSTSTAT);
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}
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} while(--loops);
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return loops?0:-2;
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}
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static int smbus_wait_until_done(void)
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{
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned char val;
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smbus_delay();
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val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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if ( (val & 1) == 0) {
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break;
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}
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if ((val & ~((1<<6)|(1<<0)) ) != 0 ) {
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break;
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}
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} while(--loops);
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return loops?0:-3;
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}
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static int smbus_read_byte(unsigned device, unsigned address)
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{
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unsigned char global_control_register;
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unsigned char global_status_register;
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unsigned char byte;
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if (smbus_wait_until_ready() < 0) {
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return -2;
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}
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/* setup transaction */
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/* disable interrupts */
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outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL);
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/* set the device I'm talking too */
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outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
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/* set the command/address... */
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outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
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/* set up for a byte data read */
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outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL);
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/* clear any lingering errors, so the transaction will run */
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outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
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/* clear the data byte...*/
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outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
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/* start a byte read, with interrupts disabled */
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outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
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/* poll for transaction completion */
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if (smbus_wait_until_done() < 0) {
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return -3;
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}
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global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1<<6); /* Ignore the In Use Status... */
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/* read results of transaction */
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byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
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if (global_status_register != 2) {
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return -1;
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}
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return byte;
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}
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#if 0
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static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
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{
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if (smbus_wait_until_ready() < 0) {
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return;
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}
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/* by LYH */
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outb(0x37,SMBUS_IO_BASE + SMBHSTSTAT);
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/* set the device I'm talking too */
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outw(((device & 0x7f) << 1) | 0, SMBUS_IO_BASE + SMBHSTADDR);
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/* data to send */
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outb(val, SMBUS_IO_BASE + SMBHSTDAT);
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outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
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/* start the command */
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outb(0xa, SMBUS_IO_BASE + SMBHSTCTL);
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/* poll for transaction completion */
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smbus_wait_until_done();
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return;
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}
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#endif
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@ -0,0 +1,53 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "i82801dbm.h"
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static void ide_init(struct device *dev)
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{
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#if ICH5_SATA_ADDRESS_MAP<=1
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/* Enable ide devices so the linux ide driver will work */
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uint16_t word;
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uint8_t byte;
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int enable_a=1, enable_b=1;
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word = pci_read_config16(dev, 0x40);
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word &= ~((1 << 15));
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if (enable_a) {
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/* Enable first ide interface */
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word |= (1<<15);
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printk_debug("IDE0 ");
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}
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pci_write_config16(dev, 0x40, word);
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word = pci_read_config16(dev, 0x42);
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word &= ~((1 << 15));
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if (enable_a) {
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/* Enable secondary ide interface */
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word |= (1<<15);
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printk_debug("IDE1 ");
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}
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pci_write_config16(dev, 0x42, word);
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#endif
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}
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static struct device_operations ide_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = ide_init,
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.scan_bus = 0,
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.enable = i82801dbm_enable,
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};
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static struct pci_driver ide_driver __pci_driver = {
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.ops = &ide_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801ER_1F1,
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};
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@ -0,0 +1,219 @@
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/*
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* (C) 2003 Linux Networx, SuSE Linux AG
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* (C) 2004 Tyan Computer
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <device/chip.h>
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#include <pc80/mc146818rtc.h>
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#include "i82801dbm.h"
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void isa_dma_init(void); /* from /pc80/isa-dma.c */
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#define NMI_OFF 0
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void i82801dbm_enable_ioapic( struct device *dev)
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{
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uint32_t dword;
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volatile uint32_t *ioapic_sba = (volatile uint32_t *)0xfec00000;
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volatile uint32_t *ioapic_sbd = (volatile uint32_t *)0xfec00010;
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dword = pci_read_config32(dev, GEN_CNTL);
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dword |= (3 << 7); /* enable ioapic */
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dword |= (1 <<13); /* coprocessor error enable */
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dword |= (1 << 1); /* delay transaction enable */
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dword |= (1 << 2); /* DMA collection buf enable */
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pci_write_config32(dev, GEN_CNTL, dword);
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printk_debug("ioapic southbridge enabled %x\n",dword);
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*ioapic_sba=0;
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*ioapic_sbd=(2<<24);
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//lyh *ioapic_sba=3;
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//lyh *ioapic_sbd=1;
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*ioapic_sba=0;
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dword=*ioapic_sbd;
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printk_debug("Southbridge apic id = %x\n",dword);
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if(dword!=(2<<24))
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for(;;);
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//lyh *ioapic_sba=3;
|
||||
//lyh dword=*ioapic_sbd;
|
||||
//lyh printk_debug("Southbridge apic DT = %x\n",dword);
|
||||
//lyh if(dword!=1)
|
||||
//lyh for(;;);
|
||||
|
||||
|
||||
}
|
||||
void i82801dbm_enable_serial_irqs( struct device *dev)
|
||||
{
|
||||
pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
|
||||
}
|
||||
void i82801dbm_lpc_route_dma( struct device *dev, uint8_t mask)
|
||||
{
|
||||
uint16_t word;
|
||||
int i;
|
||||
word = pci_read_config8(dev, PCI_DMA_CFG);
|
||||
word &= ((1 << 10) - (1 << 8));
|
||||
for(i = 0; i < 8; i++) {
|
||||
if (i == 4)
|
||||
continue;
|
||||
word |= ((mask & (1 << i))? 3:1) << (i*2);
|
||||
}
|
||||
pci_write_config16(dev, PCI_DMA_CFG, word);
|
||||
}
|
||||
void i82801dbm_rtc_init(struct device *dev)
|
||||
{
|
||||
uint8_t byte;
|
||||
uint32_t dword;
|
||||
int rtc_failed;
|
||||
byte = pci_read_config8(dev, GEN_PMCON_3);
|
||||
rtc_failed = byte & RTC_FAILED;
|
||||
if (rtc_failed) {
|
||||
byte &= ~(1 << 1); /* preserve the power fail state */
|
||||
pci_write_config8(dev, GEN_PMCON_3, byte);
|
||||
}
|
||||
dword = pci_read_config32(dev, GEN_STS);
|
||||
rtc_failed |= dword & (1 << 2);
|
||||
rtc_init(rtc_failed);
|
||||
}
|
||||
|
||||
|
||||
void i82801dbm_1f0_misc(struct device *dev)
|
||||
{
|
||||
pci_write_config16(dev, PCICMD, 0x014f);
|
||||
pci_write_config32(dev, PMBASE, 0x00001001);
|
||||
pci_write_config8(dev, ACPI_CNTL, 0x10);
|
||||
pci_write_config32(dev, GPIO_BASE, 0x00001181);
|
||||
pci_write_config8(dev, GPIO_CNTL, 0x10);
|
||||
pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
|
||||
pci_write_config8(dev, PIRQE_ROUT, 0x07);
|
||||
pci_write_config8(dev, RTC_CONF, 0x04);
|
||||
pci_write_config8(dev, COM_DEC, 0x10); //lyh E0->
|
||||
pci_write_config16(dev, LPC_EN, 0x000F); //LYH 000D->
|
||||
}
|
||||
|
||||
static void enable_hpet(struct device *dev)
|
||||
{
|
||||
const unsigned long hpet_address = 0xfed0000;
|
||||
|
||||
uint32_t dword;
|
||||
uint32_t code = (0 & 0x3);
|
||||
|
||||
dword = pci_read_config32(dev, GEN_CNTL);
|
||||
dword |= (1 << 17); /* enable hpet */
|
||||
/*Bits [16:15]Memory Address Range
|
||||
00 FED0_0000h - FED0_03FFh
|
||||
01 FED0_1000h - FED0_13FFh
|
||||
10 FED0_2000h - FED0_23FFh
|
||||
11 FED0_3000h - FED0_33FFh*/
|
||||
|
||||
dword &= ~(3 << 15); /* clear it */
|
||||
dword |= (code<<15);
|
||||
|
||||
printk_debug("enabling HPET @0x%x\n", hpet_address | (code <<12) );
|
||||
}
|
||||
|
||||
static void lpc_init(struct device *dev)
|
||||
{
|
||||
uint8_t byte;
|
||||
int pwr_on=-1;
|
||||
int nmi_option;
|
||||
|
||||
/* IO APIC initialization */
|
||||
i82801dbm_enable_ioapic(dev);
|
||||
|
||||
i82801dbm_enable_serial_irqs(dev);
|
||||
|
||||
/* posted memory write enable */
|
||||
byte = pci_read_config8(dev, 0x46);
|
||||
pci_write_config8(dev, 0x46, byte | (1<<0));
|
||||
|
||||
/* power after power fail */
|
||||
/* FIXME this doesn't work! */
|
||||
/* Which state do we want to goto after g3 (power restored)?
|
||||
* 0 == S0 Full On
|
||||
* 1 == S5 Soft Off
|
||||
*/
|
||||
pci_write_config8(dev, GEN_PMCON_3, pwr_on?0:1);
|
||||
printk_info("set power %s after power fail\n", pwr_on?"on":"off");
|
||||
#if 0
|
||||
/* Enable Error reporting */
|
||||
/* Set up sync flood detected */
|
||||
byte = pci_read_config8(dev, 0x47);
|
||||
byte |= (1 << 1);
|
||||
pci_write_config8(dev, 0x47, byte);
|
||||
#endif
|
||||
|
||||
/* Set up NMI on errors */
|
||||
byte = pci_read_config8(dev, 0x61);
|
||||
byte |= (1 << 3); /* IOCHK# NMI Enable */
|
||||
byte |= (1 << 6); /* PCI SERR# Enable */
|
||||
pci_write_config8(dev, 0x61, byte);
|
||||
byte = pci_read_config8(dev, 0x70);
|
||||
nmi_option = NMI_OFF;
|
||||
get_option(&nmi_option, "nmi");
|
||||
if (nmi_option) {
|
||||
byte |= (1 << 7); /* set NMI */
|
||||
pci_write_config8(dev, 0x70, byte);
|
||||
}
|
||||
|
||||
/* Initialize the real time clock */
|
||||
i82801dbm_rtc_init(dev);
|
||||
|
||||
i82801dbm_lpc_route_dma(dev, 0xff);
|
||||
|
||||
/* Initialize isa dma */
|
||||
isa_dma_init();
|
||||
|
||||
i82801dbm_1f0_misc(dev);
|
||||
/* Initialize the High Precision Event Timers */
|
||||
enable_hpet(dev);
|
||||
}
|
||||
|
||||
static void i82801dbm_lpc_read_resources(device_t dev)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
/* Get the normal pci resources of this device */
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* Find my place in the resource list */
|
||||
reg = dev->resources;
|
||||
|
||||
/* Add an extra subtractive resource for both memory and I/O */
|
||||
dev->resource[reg].base = 0;
|
||||
dev->resource[reg].size = 0;
|
||||
dev->resource[reg].align = 0;
|
||||
dev->resource[reg].gran = 0;
|
||||
dev->resource[reg].limit = 0;
|
||||
dev->resource[reg].flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
|
||||
dev->resource[reg].index = 0;
|
||||
reg++;
|
||||
|
||||
dev->resource[reg].base = 0;
|
||||
dev->resource[reg].size = 0;
|
||||
dev->resource[reg].align = 0;
|
||||
dev->resource[reg].gran = 0;
|
||||
dev->resource[reg].limit = 0;
|
||||
dev->resource[reg].flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
|
||||
dev->resource[reg].index = 0;
|
||||
reg++;
|
||||
|
||||
dev->resources = reg;
|
||||
}
|
||||
|
||||
static struct device_operations lpc_ops = {
|
||||
.read_resources = i82801dbm_lpc_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = lpc_init,
|
||||
.scan_bus = scan_static_bus,
|
||||
.enable = i82801dbm_enable,
|
||||
};
|
||||
|
||||
static struct pci_driver lpc_driver __pci_driver = {
|
||||
.ops = &lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_82801ER_1F0,
|
||||
};
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "i82801dbm.h"
|
||||
|
||||
|
||||
static struct device_operations nic_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = 0,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver nic_driver __pci_driver = {
|
||||
.ops = &nic_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x1051,
|
||||
};
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "i82801dbm.h"
|
||||
|
||||
static void pci_init(struct device *dev)
|
||||
{
|
||||
/* Enable pci error detecting */
|
||||
uint32_t dword;
|
||||
/* System error enable */
|
||||
dword = pci_read_config32(dev, 0x04);
|
||||
dword |= (1<<8); /* SERR# Enable */
|
||||
dword |= (1<<6); /* Parity Error Response */
|
||||
pci_write_config32(dev, 0x04, dword);
|
||||
|
||||
}
|
||||
|
||||
static struct device_operations pci_ops = {
|
||||
.read_resources = pci_bus_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_bus_enable_resources,
|
||||
.init = pci_init,
|
||||
.scan_bus = pci_scan_bridge,
|
||||
};
|
||||
|
||||
static struct pci_driver pci_driver __pci_driver = {
|
||||
.ops = &pci_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_82801ER_1E0,
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#include <arch/io.h>
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
/* Try rebooting through port 0xcf9 */
|
||||
outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
|
||||
}
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "i82801dbm.h"
|
||||
|
||||
static void sata_init(struct device *dev)
|
||||
{
|
||||
|
||||
uint16_t word;
|
||||
uint8_t byte;
|
||||
int enable_c=1, enable_d=1;
|
||||
int i;
|
||||
|
||||
//Enable Serial ATA port
|
||||
byte = pci_read_config8(dev,0x90);
|
||||
byte &= 0xf8;
|
||||
byte |= ICH5_SATA_ADDRESS_MAP & 7;
|
||||
pci_write_config8(dev,0x90,byte);
|
||||
|
||||
// for(i=0;i<10;i++) {
|
||||
word = pci_read_config16(dev,0x92);
|
||||
word &= 0xfffc;
|
||||
// if( (word & 0x0003) == 0x0003) break;
|
||||
word |= 0x0003; // enable P0/P1
|
||||
pci_write_config16(dev,0x92,word);
|
||||
// }
|
||||
|
||||
// for(i=0;i<10;i++) {
|
||||
/* enable ide0 */
|
||||
word = pci_read_config16(dev, 0x40);
|
||||
word &= ~(1 << 15);
|
||||
if(enable_c==0) {
|
||||
// if( (word & 0x8000) == 0x0000) break;
|
||||
word |= 0x0000;
|
||||
}
|
||||
else {
|
||||
// if( (word & 0x8000) == 0x8000) break;
|
||||
word |= 0x8000;
|
||||
}
|
||||
pci_write_config16(dev, 0x40, word);
|
||||
// }
|
||||
/* enable ide1 */
|
||||
// for(i=0;i<10;i++) {
|
||||
word = pci_read_config16(dev, 0x42);
|
||||
word &= ~(1 << 15);
|
||||
if(enable_d==0) {
|
||||
// if( (word & 0x8000) == 0x0000) break;
|
||||
word |= 0x0000;
|
||||
}
|
||||
else {
|
||||
// if( (word & 0x8000) == 0x8000) break;
|
||||
word |= 0x8000;
|
||||
}
|
||||
pci_write_config16(dev, 0x42, word);
|
||||
// }
|
||||
|
||||
}
|
||||
|
||||
static struct device_operations sata_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = sata_init,
|
||||
.scan_bus = 0,
|
||||
.enable = i82801dbm_enable,
|
||||
};
|
||||
|
||||
static struct pci_driver stat_driver __pci_driver = {
|
||||
.ops = &sata_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_82801ER_1F2_R,
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
#include <smbus.h>
|
||||
#include <pci.h>
|
||||
#include <arch/io.h>
|
||||
|
||||
#define PM_BUS 0
|
||||
#define PM_DEVFN PCI_DEVFN(0x1f,3)
|
||||
|
||||
#define SMBUS_IO_BASE 0x1000
|
||||
#define SMBHSTSTAT 0
|
||||
#define SMBHSTCTL 2
|
||||
#define SMBHSTCMD 3
|
||||
#define SMBHSTADD 4
|
||||
#define SMBHSTDAT0 5
|
||||
#define SMBHSTDAT1 6
|
||||
#define SMBBLKDAT 7
|
||||
|
||||
void smbus_enable(void)
|
||||
{
|
||||
unsigned char byte;
|
||||
/* iobase addr */
|
||||
pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x20, SMBUS_IO_BASE | 1);
|
||||
/* smbus enable */
|
||||
pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0x40, 1);
|
||||
/* iospace enable */
|
||||
pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1);
|
||||
|
||||
/* Disable interrupt generation */
|
||||
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
|
||||
|
||||
}
|
||||
|
||||
void smbus_setup(void)
|
||||
{
|
||||
outb(0, SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
}
|
||||
|
||||
static void smbus_wait_until_ready(void)
|
||||
{
|
||||
while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
|
||||
/* nop */
|
||||
}
|
||||
}
|
||||
|
||||
static void smbus_wait_until_done(void)
|
||||
{
|
||||
unsigned char byte;
|
||||
do {
|
||||
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
}
|
||||
while((byte &1) == 1);
|
||||
while( (byte & ~1) == 0) {
|
||||
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
}
|
||||
}
|
||||
|
||||
int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
|
||||
{
|
||||
unsigned char host_status_register;
|
||||
unsigned char byte;
|
||||
|
||||
smbus_wait_until_ready();
|
||||
|
||||
/* setup transaction */
|
||||
/* disable interrupts */
|
||||
outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
|
||||
/* set the device I'm talking too */
|
||||
outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD);
|
||||
/* set the command/address... */
|
||||
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
|
||||
/* set up for a byte data read */
|
||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
|
||||
|
||||
/* clear any lingering errors, so the transaction will run */
|
||||
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
|
||||
/* clear the data byte...*/
|
||||
outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
|
||||
|
||||
/* start the command */
|
||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
|
||||
|
||||
/* poll for transaction completion */
|
||||
smbus_wait_until_done();
|
||||
|
||||
host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
|
||||
/* read results of transaction */
|
||||
byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
|
||||
|
||||
*result = byte;
|
||||
return host_status_register != 0x02;
|
||||
}
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "i82801dbm.h"
|
||||
|
||||
static void usb_init(struct device *dev)
|
||||
{
|
||||
uint32_t cmd;
|
||||
|
||||
#if 0
|
||||
printk_debug("USB: Setting up controller.. ");
|
||||
cmd = pci_read_config32(dev, PCI_COMMAND);
|
||||
pci_write_config32(dev, PCI_COMMAND,
|
||||
cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
|
||||
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
|
||||
|
||||
|
||||
printk_debug("done.\n");
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
static struct device_operations usb_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = usb_init,
|
||||
.scan_bus = 0,
|
||||
.enable = i82801dbm_enable,
|
||||
};
|
||||
|
||||
static struct pci_driver usb_driver_1 __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_82801ER_1D0,
|
||||
};
|
||||
static struct pci_driver usb_driver_2 __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_82801ER_1D1,
|
||||
};
|
||||
static struct pci_driver usb_driver_3 __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_82801ER_1D2,
|
||||
};
|
||||
static struct pci_driver usb_driver_4 __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_82801ER_1D3,
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
//2003 Copywright Tyan
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "i82801dbm.h"
|
||||
|
||||
static void usb2_init(struct device *dev)
|
||||
{
|
||||
uint32_t cmd;
|
||||
|
||||
#if 0
|
||||
printk_debug("USB: Setting up controller.. ");
|
||||
cmd = pci_read_config32(dev, PCI_COMMAND);
|
||||
pci_write_config32(dev, PCI_COMMAND,
|
||||
cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
|
||||
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
|
||||
|
||||
|
||||
printk_debug("done.\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
static struct device_operations usb2_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = usb2_init,
|
||||
.scan_bus = 0,
|
||||
.enable = i82801dbm_enable,
|
||||
};
|
||||
|
||||
static struct pci_driver usb2_driver __pci_driver = {
|
||||
.ops = &usb2_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_82801ER_1D7,
|
||||
};
|
||||
Loading…
Reference in New Issue