post_code: add post code for critical CBFS failures
Add a new post code POST_INVALID_CBFS, used when coreboot fails to locate or validate a resource that is stored in CBFS. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: If1c8b92889040f9acd6250f847db02626809a987 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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@ -17,6 +17,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4.
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0x88 Devices have been configured
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0x89 Devices have been enabled
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0xe0 Boot media (e.g. SPI ROM) is corrupt
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0xe1 Resource stored within CBFS is corrupt
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0xf8 Entry into elf boot
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0xf3 Jumping to payload
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@ -325,6 +325,13 @@
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*/
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#define POST_INVALID_ROM 0xe0
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/**
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* \brief Invalid or corrupt CBFS
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*
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* Set if firmware failed to find or validate a resource that is stored in CBFS.
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*/
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#define POST_INVALID_CBFS 0xe1
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/**
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* \brief TPM failure
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*
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@ -116,7 +116,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version)
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/* Locate the RMU data file in flash */
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rmu_data = locate_rmu_file(&rmu_data_len);
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if (!rmu_data)
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die("Microcode file (rmu.bin) not found.");
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die_with_post_code(POST_INVALID_CBFS,
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"Microcode file (rmu.bin) not found.");
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/* Locate the configuration data from devicetree.cb */
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dev = pcidev_path_on_root(LPC_DEV_FUNC);
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