From 184329c77a7750d86cfe1d848000dae0e72a3889 Mon Sep 17 00:00:00 2001
From: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Date: Tue, 5 Sep 2023 09:08:39 +0800
Subject: [PATCH] mb/google/nissa/yaviks: Disable V1P05 control pin

Yaviks already disabled external V1P05, so disable V1P05 control pin
which controls the VCC_V1P105_EXT_1P05.

BUG=b:294456574
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I4128cfcfa5be0d141f0173e87518407331d79e8e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77645
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/yaviks/gpio.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/brya/variants/yaviks/gpio.c b/src/mainboard/google/brya/variants/yaviks/gpio.c
index 334959c7bf..19178d8187 100644
--- a/src/mainboard/google/brya/variants/yaviks/gpio.c
+++ b/src/mainboard/google/brya/variants/yaviks/gpio.c
@@ -40,6 +40,8 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_NC(GPP_F13, NONE),
 	/* F15 : GSXSRESET# ==> NC */
 	PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
+	/* F23 : V1P05EXT_CTRL ==> NC */
+	PAD_NC(GPP_F23, NONE),
 
 	/* H8  : CNV_MFUART2_RXD ==> NC */
 	PAD_NC(GPP_H8, NONE),