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mb/google/drallion: fix GPP_E16 glitch when enter S5 

Set GPP_E16 reset to DEEP.

BUG=b:143057255
BRANCH=N/A
TEST=Measure GPP_E16 from S0 to S5 has no glitch

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I63932c6f5c8b7e6e9ab8aa55e69c629d29e7d1fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36511
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Eric Lai 2019-11-01 02:01:02 +08:00 committed by Patrick Georgi
parent e979442cd6
commit 1845fc8947
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/drallion/variants/drallion/gpio.c
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@ -154,7 +154,7 @@ static const struct pad_config gpio_table[] = {
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */
/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */
/* DDPE_HPD3 */ PAD_CFG_GPO(GPP_E16, 1, PLTRST), /* HDMI_PD# */ /* DDPE_HPD3 */ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* HDMI_PD# */
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),