nb/x4x/raminit: Decode ddr3 dimms
Since this memory controller supports both DDR2 and DDR3 allow it to decode both while making the dram type mutually exclusive. Change-Id: I8dba19ca1e6e6b0a03b56c8de9633f9c1a2eb7d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans
Patrick Georgi
parent
701da39fb7
commit
1848ba3b54
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@ -33,6 +33,7 @@
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#include <spd.h>
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#include <string.h>
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#include <device/dram/ddr2.h>
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#include <device/dram/ddr3.h>
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#include <mrc_cache.h>
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#define MRC_CACHE_VERSION 0
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@ -42,11 +43,25 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
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return smbus_read_byte(device, address);
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}
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static u16 ddr2_get_crc(u8 device, u8 len)
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{
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u8 raw_spd[128] = {};
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i2c_block_read(device, 64, 9, &raw_spd[64]);
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i2c_block_read(device, 93, 6, &raw_spd[93]);
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return spd_ddr2_calc_unique_crc(raw_spd, len);
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}
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static u16 ddr3_get_crc(u8 device, u8 len)
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{
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u8 raw_spd[256] = {};
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i2c_block_read(device, 117, 11, &raw_spd[117]);
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return spd_ddr3_calc_unique_crc(raw_spd, len);
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}
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static enum cb_err verify_spds(const u8 *spd_map,
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const struct sysinfo *ctrl_cached)
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{
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int i;
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u8 raw_spd[256] = {};
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u16 crc;
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for (i = 0; i < TOTAL_DIMMS; i++) {
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@ -60,18 +75,11 @@ static enum cb_err verify_spds(const u8 *spd_map,
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== RAW_CARD_UNPOPULATED)
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return CB_ERR;
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if (ctrl_cached->spd_type == DDR2) {
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i2c_block_read(spd_map[i], 64, 9, &raw_spd[64]);
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i2c_block_read(spd_map[i], 93, 6, &raw_spd[93]);
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crc = spd_ddr2_calc_unique_crc(raw_spd, len);
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} else { /*
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* DDR3: TODO ddr2.h and ddr3.h
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* cannot be included directly
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*/
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crc = 0;
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// i2c_block_read(spd_map[i], 117, 11, &raw_spd[117]);
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// crc = spd_ddr3_calc_unique_crc(raw_spd, len);
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}
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if (ctrl_cached->spd_type == DDR2)
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crc = ddr2_get_crc(spd_map[i], len);
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else
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crc = ddr3_get_crc(spd_map[i], len);
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if (crc != ctrl_cached->dimms[i].spd_crc)
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return CB_ERR;
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}
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@ -88,6 +96,7 @@ struct abs_timings {
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u32 min_tWTR;
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u32 min_tRRD;
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u32 min_tRTP;
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u32 min_tAA;
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u32 min_tCLK_cas[8];
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u32 cas_supported;
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};
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@ -148,9 +157,6 @@ static void mchinfo_ddr2(struct sysinfo *s)
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if (!(capid & (1<<(56-32))))
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printk(BIOS_WARNING, "AMT enabled\n");
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s->max_ddr2_mhz = 800; // All chipsets in x4x support up to 800MHz DDR2
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printk(BIOS_WARNING, "Capable of DDR2 of %d MHz or lower\n", s->max_ddr2_mhz);
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if (!(capid & (1<<(48-32))))
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printk(BIOS_WARNING, "VT-d enabled\n");
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}
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@ -238,6 +244,174 @@ static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
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return CB_SUCCESS;
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}
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static void normalize_tCLK(u32 *tCLK)
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{
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if (*tCLK <= TCK_666MHZ)
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*tCLK = TCK_666MHZ;
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else if (*tCLK <= TCK_533MHZ)
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*tCLK = TCK_533MHZ;
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else if (*tCLK <= TCK_400MHZ)
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*tCLK = TCK_400MHZ;
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else
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*tCLK = 0;
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}
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static void select_cas_dramfreq_ddr3(struct sysinfo *s,
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struct abs_timings *saved_timings)
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{
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/*
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* various constraints must be fulfilled:
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* CAS * tCK < 20ns == 160MTB
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* tCK_max >= tCK >= tCK_min
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* CAS >= roundup(tAA_min/tCK)
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* CAS supported
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* AND BTW: Clock(MT) = 2000 / tCK(ns) - intel uses MTs but calls them MHz
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*/
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u32 min_tCLK;
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u8 try_CAS;
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u16 capid = (pci_read_config16(PCI_DEV(0, 0, 0), 0xea) >> 4) & 0x3f;
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switch (s->max_fsb) {
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default:
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case FSB_CLOCK_800MHz:
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min_tCLK = TCK_400MHZ;
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break;
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case FSB_CLOCK_1066MHz:
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min_tCLK = TCK_533MHZ;
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break;
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case FSB_CLOCK_1333MHz:
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min_tCLK = TCK_666MHZ;
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break;
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}
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switch (capid >> 3) {
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default: /* Should not happen */
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min_tCLK = TCK_400MHZ;
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break;
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case 1:
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min_tCLK = MAX(min_tCLK, TCK_400MHZ);
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break;
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case 2:
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min_tCLK = MAX(min_tCLK, TCK_533MHZ);
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break;
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case 3: /* Only on P45 */
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min_tCLK = MAX(min_tCLK, TCK_666MHZ);
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break;
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}
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min_tCLK = MAX(min_tCLK, saved_timings->min_tclk);
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if (min_tCLK == 0) {
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printk(BIOS_ERR, "DRAM frequency is under lowest supported "
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"frequency (400 MHz). Increasing to 400 MHz"
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"as last resort");
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min_tCLK = TCK_400MHZ;
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}
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while (1) {
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normalize_tCLK(&min_tCLK);
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if (min_tCLK == 0)
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die("Couldn't find compatible clock / CAS settings.\n");
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try_CAS = DIV_ROUND_UP(saved_timings->min_tAA, min_tCLK);
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printk(BIOS_SPEW, "Trying CAS %u, tCK %u.\n", try_CAS, min_tCLK);
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for (; try_CAS <= DDR3_MAX_CAS; try_CAS++) {
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/*
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* cas_supported is encoded like the SPD which starts
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* at CAS=4.
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*/
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if ((saved_timings->cas_supported << 4) & (1 << try_CAS))
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break;
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}
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if ((try_CAS <= DDR3_MAX_CAS) && (try_CAS * min_tCLK < 20 * 256)) {
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/* Found good CAS. */
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printk(BIOS_SPEW, "Found compatible tCLK / CAS pair: %u / %u.\n",
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min_tCLK, try_CAS);
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break;
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}
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/*
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* If no valid tCLK / CAS pair could be found for a tCLK
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* increase it after which it gets normalised. This means
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* that a lower frequency gets tried.
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*/
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min_tCLK++;
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}
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s->selected_timings.tclk = min_tCLK;
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s->selected_timings.CAS = try_CAS;
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switch (s->selected_timings.tclk) {
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case TCK_400MHZ:
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s->selected_timings.mem_clk = MEM_CLOCK_800MHz;
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break;
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case TCK_533MHZ:
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s->selected_timings.mem_clk = MEM_CLOCK_1066MHz;
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break;
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case TCK_666MHZ:
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s->selected_timings.mem_clk = MEM_CLOCK_1333MHz;
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break;
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}
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}
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static int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
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struct abs_timings *saved_timings, struct sysinfo *s)
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{
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struct dimm_attr_st decoded_dimm;
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if (spd_decode_ddr3(&decoded_dimm, raw_spd) != SPD_STATUS_OK)
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return CB_ERR;
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if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP))
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dram_print_spd_ddr3(&decoded_dimm);
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/* x4 DIMMs are not supported (true for both ddr2 and ddr3) */
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if (!(decoded_dimm.width & (0x8 | 0x10))) {
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printk(BIOS_ERR, "DIMM%d Unsupported width: x%d. Disabling dimm\n",
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dimm_idx, s->dimms[dimm_idx].width);
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return CB_ERR;
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}
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s->dimms[dimm_idx].width = (decoded_dimm.width >> 3) - 1;
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/*
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* This boils down to:
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* "Except for the x16 configuration, all DDR3 devices have a
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* 1KB page size. For the x16 configuration, the page size is 2KB
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* for all densities except the 256Mb device, which has a 1KB page size."
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* Micron, 'TN-47-16 Designing for High-Density DDR2 Memory'
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*/
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s->dimms[dimm_idx].page_size = decoded_dimm.width *
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(1 << decoded_dimm.col_bits) / 8;
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s->dimms[dimm_idx].n_banks = N_BANKS_8; /* Always 8 banks on ddr3?? */
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s->dimms[dimm_idx].ranks = decoded_dimm.ranks;
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s->dimms[dimm_idx].rows = decoded_dimm.row_bits;
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s->dimms[dimm_idx].cols = decoded_dimm.col_bits;
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saved_timings->min_tRAS =
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MAX(saved_timings->min_tRAS, decoded_dimm.tRAS);
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saved_timings->min_tRP =
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MAX(saved_timings->min_tRP, decoded_dimm.tRP);
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saved_timings->min_tRCD =
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MAX(saved_timings->min_tRCD, decoded_dimm.tRCD);
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saved_timings->min_tWR =
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MAX(saved_timings->min_tWR, decoded_dimm.tWR);
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saved_timings->min_tRFC =
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MAX(saved_timings->min_tRFC, decoded_dimm.tRFC);
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saved_timings->min_tWTR =
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MAX(saved_timings->min_tWTR, decoded_dimm.tWTR);
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saved_timings->min_tRRD =
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MAX(saved_timings->min_tRRD, decoded_dimm.tRRD);
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saved_timings->min_tRTP =
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MAX(saved_timings->min_tRTP, decoded_dimm.tRTP);
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saved_timings->min_tAA =
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MAX(saved_timings->min_tAA, decoded_dimm.tAA);
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saved_timings->cas_supported &= decoded_dimm.cas_supported;
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s->dimms[dimm_idx].spd_crc = spd_ddr3_calc_unique_crc(raw_spd,
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raw_spd[0]);
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return CB_SUCCESS;
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}
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static void select_discrete_timings(struct sysinfo *s,
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const struct abs_timings *timings)
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{
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@ -332,15 +506,14 @@ static void decode_spd_select_timings(struct sysinfo *s)
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die("Mixing up dimm types is not supported!\n");
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printk(BIOS_DEBUG, "Decoding dimm %d\n", i);
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if (i2c_block_read(device, 0, 128, raw_spd) != 128) {
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printk(BIOS_DEBUG, "i2c block operation failed,"
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" trying smbus byte operation.\n");
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for (j = 0; j < 128; j++)
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raw_spd[j] = spd_read_byte(device, j);
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}
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if (s->spd_type == DDR2){
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printk(BIOS_DEBUG,
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"Reading SPD using i2c block operation.\n");
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if (i2c_block_read(device, 0, 128, raw_spd) != 128) {
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printk(BIOS_DEBUG, "i2c block operation failed,"
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" trying smbus byte operation.\n");
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for (j = 0; j < 128; j++)
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raw_spd[j] = spd_read_byte(device, j);
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}
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if (ddr2_save_dimminfo(i, raw_spd, &saved_timings, s)) {
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printk(BIOS_WARNING,
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"Encountered problems with SPD, "
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@ -348,8 +521,15 @@ static void decode_spd_select_timings(struct sysinfo *s)
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s->dimms[i].card_type = RAW_CARD_UNPOPULATED;
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continue;
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}
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} else { /* DDR3: not implemented so don't decode */
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die("DDR3 support is not implemented\n");
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} else { /* DDR3 */
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if (ddr3_save_dimminfo(i, raw_spd, &saved_timings, s)) {
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printk(BIOS_WARNING,
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"Encountered problems with SPD, "
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"skipping this DIMM.\n");
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/* something in decoded SPD was unsupported */
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s->dimms[i].card_type = RAW_CARD_UNPOPULATED;
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continue;
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}
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}
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dimm_mask |= (1 << i);
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}
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@ -358,6 +538,8 @@ static void decode_spd_select_timings(struct sysinfo *s)
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if (s->spd_type == DDR2)
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select_cas_dramfreq_ddr2(s, &saved_timings);
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else
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select_cas_dramfreq_ddr3(s, &saved_timings);
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select_discrete_timings(s, &saved_timings);
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}
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@ -322,7 +322,6 @@ struct rcven_timings {
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/* The setup is up to two DIMMs per channel */
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struct sysinfo {
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int boot_path;
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int max_ddr2_mhz;
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enum fsb_clock max_fsb;
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int dimm_config[2];
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