GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/amd/mayan: Enable the DT and M.2 SSD1 PCIE slots 

Program the EC GPIOs to enable the DT or M.2 SSD1
PCIe slots based on the config option selected.


Change-Id: Id141e5e55ef6e25722b411975a59c9764b86f624
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
Anand Vaikar 2023-03-29 12:46:33 +05:30 committed by Felix Held
parent 40c740584b
commit 1855cb4644
3 changed files with 55 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/mainboard/amd/mayan/Kconfig
View File

@ -80,6 +80,24 @@ config CHROMEOS
# We don't have recovery buttons, so we can't manually enable devmode.
select GBB_FLAG_FORCE_DEV_SWITCH_ON
choice
prompt "DT SLOT/M.2 SSD1 ENABLE"
default ENABLE_DT_SLOT_MAYAN
help
Either DT slot or M.2 SSD1 can be used to boot on Mayan,
as they are sharing IO lanes.
config ENABLE_DT_SLOT_MAYAN
bool "Enable DT slot"
config ENABLE_M2_SSD1_MAYAN
bool "Enable M.2 SSD1"
config DISABLE_DT_M2_MAYAN
bool "Disable both DT and M.2 slot"
endchoice
if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig
config EFS_SPI_READ_MODE
default 3 # Quad IO (1-1-4)

39
src/mainboard/amd/mayan/ec.c
View File

@ -17,6 +17,7 @@
#define EC_GPIO_3_ADDR 0xA3
#define EC_GPIO_EVAL_RST_AUX BIT(0)
#define EC_GPIO_LOM_RESET_AUX BIT(1)
#define EC_GPIO_DT_RESET_AUX BIT(2)
#define EC_GPIO_7_ADDR 0xA7
#define EC_GPIO_DT_PWREN BIT(2)
@ -25,6 +26,9 @@
#define EC_GPIO_8_ADDR 0xA8
#define EC_GPIO_SMBUS0_EN BIT(0)
#define EC_GPIO_9_ADDR 0xA9
#define EC_GPIO_M2SSD1_PWREN BIT(5)
#define EC_GPIO_A_ADDR 0xAA
#define EC_GPIO_WWAN_PWREN BIT(3)
#define EC_GPIO_M2_SSD0_PWREN BIT(6)
@ -34,6 +38,7 @@
#define EC_GPIO_DT_N_WLAN_SW BIT(1)
#define EC_GPIO_MP2_SEL BIT(2)
#define EC_GPIO_WWAN_N_LOM_SW BIT(3)
#define EC_GPIO_M2SSD1_HDD_SW BIT(6)
#define EC_SW02_ADDR 0xB7
#define EC_SW02_MS BIT(7)
@ -42,8 +47,7 @@ static void configure_ec_gpio(void)
{
uint8_t tmp;
/* Enable MXM slot: set EC_GPIO_EVAL_PWREN, EC_GPIO_EVAL_SLOT_PWR
and EC_GPIO_EVAL_RST_AUX */
/* Enable MXM slot */
tmp = ec_read(EC_GPIO_1_ADDR);
tmp |= EC_GPIO_EVAL_PWREN;
ec_write(EC_GPIO_1_ADDR, tmp);
@ -54,22 +58,51 @@ static void configure_ec_gpio(void)
tmp = ec_read(EC_GPIO_3_ADDR);
tmp |= EC_GPIO_LOM_RESET_AUX | EC_GPIO_EVAL_RST_AUX;
tmp |= EC_GPIO_LOM_RESET_AUX;
/* Enable DT slot */
if (CONFIG(ENABLE_DT_SLOT_MAYAN))
tmp |= EC_GPIO_DT_RESET_AUX;
else
tmp &= (~EC_GPIO_DT_RESET_AUX);
ec_write(EC_GPIO_3_ADDR, tmp);
tmp = ec_read(EC_GPIO_7_ADDR);
tmp |= EC_GPIO_WWAN_MODULE_RST | EC_GPIO_DT_PWREN;
tmp |= EC_GPIO_WWAN_MODULE_RST;
if (CONFIG(ENABLE_DT_SLOT_MAYAN))
tmp |= EC_GPIO_DT_PWREN;
else
tmp &= (~EC_GPIO_DT_PWREN);
ec_write(EC_GPIO_7_ADDR, tmp);
tmp = ec_read(EC_GPIO_8_ADDR);
tmp |= EC_GPIO_SMBUS0_EN;
ec_write(EC_GPIO_8_ADDR, tmp);
tmp = ec_read(EC_GPIO_9_ADDR);
/* Enable M2 SSD1 slot */
if (CONFIG(ENABLE_M2_SSD1_MAYAN))
tmp |= EC_GPIO_M2SSD1_PWREN;
else
tmp &= (~EC_GPIO_M2SSD1_PWREN);
ec_write(EC_GPIO_9_ADDR, tmp);
tmp = ec_read(EC_GPIO_A_ADDR);
tmp |= EC_GPIO_M2_SSD0_PWREN | EC_GPIO_LOM_PWREN | EC_GPIO_WWAN_PWREN;
ec_write(EC_GPIO_A_ADDR, tmp);
tmp = ec_read(EC_GPIO_C_ADDR);
tmp |= EC_GPIO_WWAN_N_LOM_SW | EC_GPIO_MP2_SEL | EC_GPIO_DT_N_WLAN_SW;
if (CONFIG(ENABLE_DT_SLOT_MAYAN)) {
tmp |= EC_GPIO_M2SSD1_HDD_SW;
tmp &= (~EC_GPIO_DT_N_WLAN_SW);
}
if (CONFIG(ENABLE_M2_SSD1_MAYAN)) {
tmp |= EC_GPIO_DT_N_WLAN_SW;
tmp &= (~EC_GPIO_M2SSD1_HDD_SW);
}
ec_write(EC_GPIO_C_ADDR, tmp);
tmp = ec_read(EC_SW02_ADDR);

3
src/mainboard/amd/mayan/port_descriptors.c
View File

@ -71,7 +71,7 @@ static const fsp_dxio_descriptor mayan_dxio_descriptors[] = {
{
// DT
.engine_type = PCIE_ENGINE,
.port_present = true,
.port_present = !CONFIG(DISABLE_DT_M2_MAYAN),
.start_lane = 8,
.end_lane = 9,
.device_number = 1,
@ -157,7 +157,6 @@ void mainboard_get_dxio_ddi_descriptors(
const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
{
mayan_ddi_descriptors[1].connector_type = get_ddi1_type();
*dxio_descs = mayan_dxio_descriptors;
*dxio_num = ARRAY_SIZE(mayan_dxio_descriptors);
*ddi_descs = mayan_ddi_descriptors;