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device/dram/ddr3: Rename DDR3 SPD memory types 

To avoid name clashes with definitions for other DRAM generations,
rename the enum type and values to contain `ddr3` or `DDR3`.

Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51896
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-03-28 13:49:39 +02:00
parent afb3d7e7ec
commit 18571389d5
3 changed files with 34 additions and 34 deletions
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20
src/device/dram/ddr3.c
View File

@ -27,11 +27,11 @@
* *
* @param type DIMM type. This is byte[3] of the SPD. * @param type DIMM type. This is byte[3] of the SPD.
*/ */
int spd_dimm_is_registered_ddr3(enum spd_dimm_type type) int spd_dimm_is_registered_ddr3(enum spd_dimm_type_ddr3 type)
{ {
if ((type == SPD_DIMM_TYPE_RDIMM) if ((type == SPD_DDR3_DIMM_TYPE_RDIMM)
| (type == SPD_DIMM_TYPE_MINI_RDIMM) | (type == SPD_DDR3_DIMM_TYPE_MINI_RDIMM)
| (type == SPD_DIMM_TYPE_72B_SO_RDIMM)) | (type == SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM))
return 1; return 1;
return 0; return 0;
@ -544,22 +544,22 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot,
dimm->mod_id = info->manufacturer_id; dimm->mod_id = info->manufacturer_id;
switch (info->dimm_type) { switch (info->dimm_type) {
case SPD_DIMM_TYPE_SO_DIMM: case SPD_DDR3_DIMM_TYPE_SO_DIMM:
dimm->mod_type = SPD_SODIMM; dimm->mod_type = SPD_SODIMM;
break; break;
case SPD_DIMM_TYPE_72B_SO_CDIMM: case SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM:
dimm->mod_type = SPD_72B_SO_CDIMM; dimm->mod_type = SPD_72B_SO_CDIMM;
break; break;
case SPD_DIMM_TYPE_72B_SO_RDIMM: case SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM:
dimm->mod_type = SPD_72B_SO_RDIMM; dimm->mod_type = SPD_72B_SO_RDIMM;
break; break;
case SPD_DIMM_TYPE_UDIMM: case SPD_DDR3_DIMM_TYPE_UDIMM:
dimm->mod_type = SPD_UDIMM; dimm->mod_type = SPD_UDIMM;
break; break;
case SPD_DIMM_TYPE_RDIMM: case SPD_DDR3_DIMM_TYPE_RDIMM:
dimm->mod_type = SPD_RDIMM; dimm->mod_type = SPD_RDIMM;
break; break;
case SPD_DIMM_TYPE_UNDEFINED: case SPD_DDR3_DIMM_TYPE_UNDEFINED:
default: default:
dimm->mod_type = SPD_UNDEFINED; dimm->mod_type = SPD_UNDEFINED;
break; break;

36
src/include/device/dram/ddr3.h
View File

@ -51,23 +51,23 @@
* Module type (byte 3, bits 3:0) of SPD * Module type (byte 3, bits 3:0) of SPD
* This definition is specific to DDR3. DDR2 SPDs have a different structure. * This definition is specific to DDR3. DDR2 SPDs have a different structure.
*/ */
enum spd_dimm_type { enum spd_dimm_type_ddr3 {
SPD_DIMM_TYPE_UNDEFINED = 0x00, SPD_DDR3_DIMM_TYPE_UNDEFINED = 0x00,
SPD_DIMM_TYPE_RDIMM = 0x01, SPD_DDR3_DIMM_TYPE_RDIMM = 0x01,
SPD_DIMM_TYPE_UDIMM = 0x02, SPD_DDR3_DIMM_TYPE_UDIMM = 0x02,
SPD_DIMM_TYPE_SO_DIMM = 0x03, SPD_DDR3_DIMM_TYPE_SO_DIMM = 0x03,
SPD_DIMM_TYPE_MICRO_DIMM = 0x04, SPD_DDR3_DIMM_TYPE_MICRO_DIMM = 0x04,
SPD_DIMM_TYPE_MINI_RDIMM = 0x05, SPD_DDR3_DIMM_TYPE_MINI_RDIMM = 0x05,
SPD_DIMM_TYPE_MINI_UDIMM = 0x06, SPD_DDR3_DIMM_TYPE_MINI_UDIMM = 0x06,
SPD_DIMM_TYPE_MINI_CDIMM = 0x07, SPD_DDR3_DIMM_TYPE_MINI_CDIMM = 0x07,
SPD_DIMM_TYPE_72B_SO_UDIMM = 0x08, SPD_DDR3_DIMM_TYPE_72B_SO_UDIMM = 0x08,
SPD_DIMM_TYPE_72B_SO_RDIMM = 0x09, SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM = 0x09,
SPD_DIMM_TYPE_72B_SO_CDIMM = 0x0a, SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM = 0x0a,
SPD_DIMM_TYPE_LRDIMM = 0x0b, SPD_DDR3_DIMM_TYPE_LRDIMM = 0x0b,
SPD_DIMM_TYPE_16B_SO_DIMM = 0x0c, SPD_DDR3_DIMM_TYPE_16B_SO_DIMM = 0x0c,
SPD_DIMM_TYPE_32B_SO_DIMM = 0x0d, SPD_DDR3_DIMM_TYPE_32B_SO_DIMM = 0x0d,
/* Masks to bits 3:0 to give the dimm type */ /* Masks to bits 3:0 to give the dimm type */
SPD_DIMM_TYPE_MASK = 0x0f, SPD_DDR3_DIMM_TYPE_MASK = 0x0f,
}; };
/** /**
@ -120,7 +120,7 @@ union dimm_flags_ddr3_st {
*/ */
struct dimm_attr_ddr3_st { struct dimm_attr_ddr3_st {
enum spd_memory_type dram_type; enum spd_memory_type dram_type;
enum spd_dimm_type dimm_type; enum spd_dimm_type_ddr3 dimm_type;
u16 cas_supported; u16 cas_supported;
/* Flags extracted from SPD */ /* Flags extracted from SPD */
union dimm_flags_ddr3_st flags; union dimm_flags_ddr3_st flags;
@ -173,7 +173,7 @@ typedef u8 spd_raw_data[256];
u16 spd_ddr3_calc_crc(u8 *spd, int len); u16 spd_ddr3_calc_crc(u8 *spd, int len);
u16 spd_ddr3_calc_unique_crc(u8 *spd, int len); u16 spd_ddr3_calc_unique_crc(u8 *spd, int len);
int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd_data); int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd_data);
int spd_dimm_is_registered_ddr3(enum spd_dimm_type type); int spd_dimm_is_registered_ddr3(enum spd_dimm_type_ddr3 type);
void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm); void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm);
int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm,
spd_raw_data spd, spd_raw_data spd,

12
src/soc/intel/common/smbios.c
View File

@ -17,22 +17,22 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type,
dimm->mod_id = mod_id; dimm->mod_id = mod_id;
/* Translate to DDR2 module type field that SMBIOS code expects. */ /* Translate to DDR2 module type field that SMBIOS code expects. */
switch (mod_type) { switch (mod_type) {
case SPD_DIMM_TYPE_SO_DIMM: case SPD_DDR3_DIMM_TYPE_SO_DIMM:
dimm->mod_type = SPD_SODIMM; dimm->mod_type = SPD_SODIMM;
break; break;
case SPD_DIMM_TYPE_72B_SO_CDIMM: case SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM:
dimm->mod_type = SPD_72B_SO_CDIMM; dimm->mod_type = SPD_72B_SO_CDIMM;
break; break;
case SPD_DIMM_TYPE_72B_SO_RDIMM: case SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM:
dimm->mod_type = SPD_72B_SO_RDIMM; dimm->mod_type = SPD_72B_SO_RDIMM;
break; break;
case SPD_DIMM_TYPE_UDIMM: case SPD_DDR3_DIMM_TYPE_UDIMM:
dimm->mod_type = SPD_UDIMM; dimm->mod_type = SPD_UDIMM;
break; break;
case SPD_DIMM_TYPE_RDIMM: case SPD_DDR3_DIMM_TYPE_RDIMM:
dimm->mod_type = SPD_RDIMM; dimm->mod_type = SPD_RDIMM;
break; break;
case SPD_DIMM_TYPE_UNDEFINED: case SPD_DDR3_DIMM_TYPE_UNDEFINED:
default: default:
dimm->mod_type = SPD_UNDEFINED; dimm->mod_type = SPD_UNDEFINED;
break; break;