diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 63fe463310..b985be20a9 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -150,6 +150,7 @@ config DRIVER_TPM_I2C_ADDR
 
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-serger.fmd" if BOARD_GOOGLE_BRASK
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa-16MiB-debugfsp.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_16384 && BUILDING_WITH_DEBUG_FSP
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa-16MiB.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_16384
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa-32MiB.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_32768
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd"
diff --git a/src/mainboard/google/brya/chromeos-nissa-16MiB-debugfsp.fmd b/src/mainboard/google/brya/chromeos-nissa-16MiB-debugfsp.fmd
new file mode 100644
index 0000000000..f4909c2455
--- /dev/null
+++ b/src/mainboard/google/brya/chromeos-nissa-16MiB-debugfsp.fmd
@@ -0,0 +1,50 @@
+FLASH 16M {
+	SI_ALL 3776K {
+		SI_DESC 4K
+		SI_ME {
+			CSE_LAYOUT 8K
+			CSE_RO 1360K
+			CSE_DATA 420K
+			# 64-KiB aligned to optimize RW erases during CSE update.
+			CSE_RW 1984K
+		}
+	}
+	SI_BIOS 12608K {
+		RW_SECTION_A 4180K {
+			VBLOCK_A 8K
+			FW_MAIN_A(CBFS)
+			RW_FWID_A 64
+			ME_RW_A(CBFS) 1434K
+		}
+		RW_MISC 152K {
+			UNIFIED_MRC_CACHE(PRESERVE) 128K {
+				RECOVERY_MRC_CACHE 64K
+				RW_MRC_CACHE 64K
+			}
+			RW_ELOG(PRESERVE) 4K
+			RW_SHARED 4K {
+				SHARED_DATA 4K
+			}
+			RW_VPD(PRESERVE) 8K
+			RW_NVRAM(PRESERVE) 8K
+		}
+		RW_SECTION_B 4180K {
+			VBLOCK_B 8K
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 64
+			ME_RW_B(CBFS) 1434K
+		}
+		# Make WP_RO region align with SPI vendor
+		# memory protected range specification.
+		WP_RO 4M {
+			RO_VPD(PRESERVE) 16K
+			RO_GSCVD 8K
+			RO_SECTION {
+				FMAP 2K
+				RO_FRID 64
+				GBB@4K 12K
+				COREBOOT(CBFS)
+			}
+		}
+	}
+}