mb/purism/librem_l1um_v2: Use chipset dt reference names
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: Id592241a1dc33559115800da10a57a5fc10867f9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
This commit is contained in:
Felix Singer
Felix Singer
parent
1b0114b3e9
commit
185ff285f6
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@ -40,20 +40,20 @@ chip soc/intel/cannonlake
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 01.0 on # PCIE6 - x16 or x8
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device ref system_agent on end
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device ref peg0 on # x16 or x8
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register "PcieClkSrcUsage[3]" = "0x40"
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smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "PCIE6" "SlotDataBusWidth16X"
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end
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device pci 01.1 on # PCIE4 - x8
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device ref peg1 on # x8
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register "PcieClkSrcUsage[4]" = "0x41"
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smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthOther" "PCIE4" "SlotDataBusWidth8X"
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end
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 off end # SA Thermal Device
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device pci 08.0 on end # Gaussian Mixture
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device pci 12.0 on end # Thermal Subsystem
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device pci 14.0 on # USB xHCI
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device ref igpu on end
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device ref dptf off end
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device ref gna on end
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device ref thermal on end
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device ref xhci on
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 front left
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register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 front right
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB_1_2 header port A
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@ -176,20 +176,20 @@ chip soc/intel/cannonlake
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end
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end
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end
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # RAM controller
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device pci 14.3 off end
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device pci 14.5 off end # SDCard
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device pci 15.0 off end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE Redirection
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 on
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device ref xdci off end
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device ref shared_sram on end
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device ref cnvi_wifi off end
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device ref sdxc off end
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device ref i2c0 off end
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device ref i2c1 off end
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device ref i2c2 off end
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device ref i2c3 off end
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device ref heci1 off end
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device ref heci2 off end
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device ref csme_ider off end
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device ref csme_ktr off end
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device ref heci3 off end
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device ref sata on
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register "satapwroptimize" = "1"
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register "SataPortsEnable[0]" = "1"
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@ -209,22 +209,22 @@ chip soc/intel/cannonlake
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register "SataPortsHotPlug[5]" = "1"
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register "SataPortsHotPlug[6]" = "1"
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register "SataPortsHotPlug[7]" = "1"
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end # SATA
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device pci 1b.4 on # PCI Express Port 21 - PCIE5
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end
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device ref pcie_rp21 on
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register "PcieRpSlotImplemented[20]" = "1"
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register "PcieRpEnable[20]" = "1"
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register "PcieRpLtrEnable[20]" = "1"
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register "PcieClkSrcUsage[10]" = "20"
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smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "PCIE5" "SlotDataBusWidth4X"
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end
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device pci 1c.0 on # PCI Express Port 1 - M2_1
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device ref pcie_rp1 on
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register "PcieRpSlotImplemented[0]" = "1"
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register "PcieRpEnable[0]" = "1"
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register "PcieRpLtrEnable[0]" = "1"
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register "PcieClkSrcUsage[1]" = "0x80"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X"
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end
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device pci 1d.0 on # PCI Express Port 9 - GbE #1
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device ref pcie_rp9 on # GbE #1
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[14]" = "8"
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@ -237,12 +237,12 @@ chip soc/intel/cannonlake
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smbios_dev_info 1
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end
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end
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device pci 1d.1 on # PCI Express Port 10 - BMC video
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device ref pcie_rp10 on # BMC video
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register "PcieRpEnable[9]" = "1"
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register "PcieRpLtrEnable[9]" = "1"
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register "PcieClkSrcUsage[8]" = "9"
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end
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device pci 1d.2 on # PCI Express Port 11 - GbE #2
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device ref pcie_rp11 on # GbE #2
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register "PcieRpEnable[10]" = "1"
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register "PcieRpLtrEnable[10]" = "1"
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register "PcieClkSrcUsage[11]" = "10"
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@ -250,11 +250,11 @@ chip soc/intel/cannonlake
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smbios_dev_info 2
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end
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end
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on # LPC Interface
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device ref uart0 off end
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device ref uart1 off end
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device ref gspi0 off end
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device ref gspi1 off end
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device ref lpc_espi on
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# This board has a lot of SuperIO LDNs with I/O BARs, the LPC generic
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# I/O ranges must be configured manually.
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register "gen1_dec" = "0x000c0ca1" # IPMI: ca0-caf
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@ -385,10 +385,10 @@ chip soc/intel/cannonlake
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device pnp 0c31.0 on end
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end
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end
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device pci 1f.1 off end # P2SB
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device pci 1f.2 hidden end # PMC
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device pci 1f.3 off end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # SPI
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device ref p2sb off end
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device ref pmc hidden end
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device ref hda off end
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device ref smbus on end
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device ref fast_spi on end
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end
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end
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