Various coding style fixes, constification, fixed typos (trivial).
Also, s/0xFF80/0xFFC0/ in the Acorp 6A815EPD board-enable, as per http://www.linuxbios.org/pipermail/linuxbios/2007-December/027750.html Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
17e993214f
commit
186a3875dc
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@ -50,13 +50,13 @@ static void w836xx_ext_leave(uint16_t port)
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static unsigned char wbsio_read(uint16_t index, uint8_t reg)
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{
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outb(reg, index);
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return inb(index+1);
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return inb(index + 1);
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}
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static void wbsio_write(uint16_t index, uint8_t reg, uint8_t data)
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{
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outb(reg, index);
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outb(data, index+1);
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outb(data, index + 1);
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}
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static void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask)
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@ -64,8 +64,8 @@ static void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask)
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uint8_t tmp;
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outb(reg, index);
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tmp = inb(index+1) & ~mask;
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outb(tmp | (data & mask), index+1);
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tmp = inb(index + 1) & ~mask;
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outb(tmp | (data & mask), index + 1);
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}
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/**
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@ -79,8 +79,8 @@ static int w83627hf_gpio24_raise(uint16_t index, const char *name)
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{
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w836xx_ext_enter(index);
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/* Is this the w83627hf? */
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if (wbsio_read(index, 0x20) != 0x52) { /* Super I/O device ID register */
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/* Is this the W83627HF? */
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if (wbsio_read(index, 0x20) != 0x52) { /* Super I/O device ID reg. */
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fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
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name, wbsio_read(index, 0x20));
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w836xx_ext_leave(index);
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@ -90,14 +90,12 @@ static int w83627hf_gpio24_raise(uint16_t index, const char *name)
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/* PIN89S: WDTO/GP24 multiplex -> GPIO24 */
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wbsio_mask(index, 0x2B, 0x10, 0x10);
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wbsio_write(index, 0x07, 0x08); /* Select logical device 8: GPIO port 2 */
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/* Select logical device 8: GPIO port 2 */
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wbsio_write(index, 0x07, 0x08);
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wbsio_mask(index, 0x30, 0x01, 0x01); /* Activate logical device. */
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wbsio_mask(index, 0xF0, 0x00, 0x10); /* GPIO24 -> output */
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wbsio_mask(index, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */
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wbsio_mask(index, 0xF1, 0x10, 0x10); /* Raise GPIO24 */
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w836xx_ext_leave(index);
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@ -107,6 +105,7 @@ static int w83627hf_gpio24_raise(uint16_t index, const char *name)
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static int w83627hf_gpio24_raise_2e(const char *name)
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{
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/* TODO: Typo? Shouldn't this be 0x2e? */
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return w83627hf_gpio24_raise(0x2d, name);
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}
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@ -119,8 +118,9 @@ static int w83627hf_gpio24_raise_2e(const char *name)
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static int w83627thf_gpio4_4_raise(uint16_t index, const char *name)
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{
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w836xx_ext_enter(index);
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/* Is this the w83627thf? */
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if (wbsio_read(index, 0x20) != 0x82) { /* Super I/O device ID register */
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/* Is this the W83627THF? */
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if (wbsio_read(index, 0x20) != 0x82) { /* Super I/O device ID reg. */
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fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n",
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name, wbsio_read(index, 0x20));
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w836xx_ext_leave(index);
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@ -129,15 +129,11 @@ static int w83627thf_gpio4_4_raise(uint16_t index, const char *name)
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/* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */
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wbsio_write(index, 0x07, 0x09); /* Select logical device 9: GPIO port 4 */
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wbsio_mask(index, 0x30, 0x02, 0x02); /* Activate logical device. */
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wbsio_mask(index, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */
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wbsio_mask(index, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */
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wbsio_mask(index, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */
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wbsio_write(index, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */
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wbsio_mask(index, 0x30, 0x02, 0x02); /* Activate logical device. */
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wbsio_mask(index, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */
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wbsio_mask(index, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */
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wbsio_mask(index, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */
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w836xx_ext_leave(index);
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@ -146,8 +142,9 @@ static int w83627thf_gpio4_4_raise(uint16_t index, const char *name)
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static int w83627thf_gpio4_4_raise_4e(const char *name)
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{
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return w83627thf_gpio4_4_raise(0x4E, name);
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return w83627thf_gpio4_4_raise(0x4e, name);
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}
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/**
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* Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
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*
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@ -156,7 +153,7 @@ static int w83627thf_gpio4_4_raise_4e(const char *name)
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static int board_via_epia_m(const char *name)
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{
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struct pci_dev *dev;
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unsigned int base;
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uint16_t base;
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uint8_t val;
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dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
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@ -173,7 +170,7 @@ static int board_via_epia_m(const char *name)
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/* Get Power Management IO address. */
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base = pci_read_word(dev, 0x88) & 0xFF80;
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/* enable GPIO15 which is connected to write protect. */
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/* Enable GPIO15 which is connected to write protect. */
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val = inb(base + 0x4D);
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val |= 0x80;
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outb(val, base + 0x4D);
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@ -199,16 +196,16 @@ static int board_asus_a7v8x_mx(const char *name)
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return -1;
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}
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/* This bit is marked reserved actually */
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/* This bit is marked reserved actually. */
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val = pci_read_byte(dev, 0x59);
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val &= 0x7F;
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pci_write_byte(dev, 0x59, val);
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/* Raise ROM MEMW# line on Winbond w83697 SuperIO */
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/* Raise ROM MEMW# line on Winbond W83697 Super I/O. */
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w836xx_ext_enter(0x2E);
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if (!(wbsio_read(0x2E, 0x24) & 0x02)) /* flash rom enabled? */
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wbsio_mask(0x2E, 0x24, 0x08, 0x08); /* enable MEMW# */
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if (!(wbsio_read(0x2E, 0x24) & 0x02)) /* Flash ROM enabled? */
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wbsio_mask(0x2E, 0x24, 0x08, 0x08); /* Enable MEMW#. */
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w836xx_ext_leave(0x2E);
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@ -323,7 +320,7 @@ static int board_epox_ep_bx3(const char *name)
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}
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/**
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* Suited for Acorp 6A815EPD
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* Suited for Acorp 6A815EPD.
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*/
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static int board_acorp_6a815epd(const char *name)
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{
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@ -338,7 +335,7 @@ static int board_acorp_6a815epd(const char *name)
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}
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/* Use GPIOBASE register to find where the GPIO is mapped. */
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port = (pci_read_word(dev, 0x58) & 0xFF80) + 0xE;
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port = (pci_read_word(dev, 0x58) & 0xFFC0) + 0xE;
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val = inb(port);
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val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */
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@ -357,25 +354,25 @@ static int board_acorp_6a815epd(const char *name)
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* Keep the second set NULLed if it should be ignored.
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*/
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struct board_pciid_enable {
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/* Any device, but make it sensible, like the isa bridge. */
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/* Any device, but make it sensible, like the ISA bridge. */
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uint16_t first_vendor;
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uint16_t first_device;
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uint16_t first_card_vendor;
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uint16_t first_card_device;
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/* Any device, but make it sensible, like
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* the host bridge. May be NULL
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* the host bridge. May be NULL.
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*/
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uint16_t second_vendor;
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uint16_t second_device;
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uint16_t second_card_vendor;
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uint16_t second_card_device;
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/* From linuxbios table */
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char *lb_vendor;
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char *lb_part;
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/* The vendor / part name from the LinuxBIOS table. */
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const char *lb_vendor;
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const char *lb_part;
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char *name;
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const char *name;
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int (*enable) (const char *name);
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};
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@ -411,8 +408,7 @@ struct board_pciid_enable board_pciid_enables[] = {
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* Match boards on LinuxBIOS table gathered vendor and part name.
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* Require main PCI IDs to match too as extra safety.
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*/
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static struct board_pciid_enable *board_match_linuxbios_name(char *vendor,
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char *part)
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static struct board_pciid_enable *board_match_linuxbios_name(const char *vendor, const char *part)
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{
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struct board_pciid_enable *board = board_pciid_enables;
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@ -431,7 +427,9 @@ static struct board_pciid_enable *board_match_linuxbios_name(char *vendor,
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continue;
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return board;
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}
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printf("NOT FOUND %s:%s\n", vendor, part);
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return NULL;
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}
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@ -472,7 +470,7 @@ static struct board_pciid_enable *board_match_pci_card_ids(void)
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return NULL;
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}
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int board_flash_enable(char *vendor, char *part)
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int board_flash_enable(const char *vendor, const char *part)
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{
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struct board_pciid_enable *board = NULL;
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int ret = 0;
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@ -34,12 +34,14 @@
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#include <unistd.h>
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#include "flash.h"
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static int enable_flash_ali_m1533(struct pci_dev *dev, char *name)
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static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
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{
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uint8_t tmp;
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/* ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
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0xFFFE0000-0xFFFFFFFF ROM select enable. */
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/*
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* ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
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* 0xFFFE0000-0xFFFFFFFF ROM select enable.
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*/
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tmp = pci_read_byte(dev, 0x47);
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tmp |= 0x46;
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pci_write_byte(dev, 0x47, tmp);
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@ -47,24 +49,28 @@ static int enable_flash_ali_m1533(struct pci_dev *dev, char *name)
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return 0;
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}
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static int enable_flash_sis630(struct pci_dev *dev, char *name)
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static int enable_flash_sis630(struct pci_dev *dev, const char *name)
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{
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char b;
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uint8_t b;
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/* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630 */
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/* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
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b = pci_read_byte(dev, 0x40);
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pci_write_byte(dev, 0x40, b | 0xb);
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/* Flash write enable on SiS 540/630 */
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/* Flash write enable on SiS 540/630. */
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b = pci_read_byte(dev, 0x45);
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pci_write_byte(dev, 0x45, b | 0x40);
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/* The same thing on SiS 950 SuperIO side */
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/* The same thing on SiS 950 Super I/O side... */
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/* First probe for Super I/O on config port 0x2e. */
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outb(0x87, 0x2e);
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outb(0x01, 0x2e);
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outb(0x55, 0x2e);
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outb(0x55, 0x2e);
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if (inb(0x2f) != 0x87) {
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/* If that failed, try config port 0x4e. */
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outb(0x87, 0x4e);
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outb(0x01, 0x4e);
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outb(0x55, 0x4e);
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@ -99,7 +105,7 @@ static int enable_flash_sis630(struct pci_dev *dev, char *name)
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* - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
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* - Order Number: 290562-001
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*/
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static int enable_flash_piix4(struct pci_dev *dev, char *name)
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static int enable_flash_piix4(struct pci_dev *dev, const char *name)
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{
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uint16_t old, new;
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uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
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@ -132,23 +138,19 @@ static int enable_flash_piix4(struct pci_dev *dev, char *name)
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return 0;
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}
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static int enable_flash_ich(struct pci_dev *dev, char *name, int bios_cntl)
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/*
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* See ie. page 375 of "Intel ICH7 External Design Specification"
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* http://download.intel.com/design/chipsets/datashts/30701302.pdf
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*/
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static int enable_flash_ich(struct pci_dev *dev, const char *name,
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int bios_cntl)
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{
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/* register 4e.b gets or'ed with one */
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uint8_t old, new;
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/* if it fails, it fails. There are so many variations of broken mobos
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* that it is hard to argue that we should quit at this point.
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*/
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/* Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
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/*
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* Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
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* just treating it as 8 bit wide seems to work fine in practice.
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*/
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/* see ie. page 375 of "Intel ICH7 External Design Specification"
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* http://download.intel.com/design/chipsets/datashts/30701302.pdf
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*/
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old = pci_read_byte(dev, bios_cntl);
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new = old | 1;
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@ -166,17 +168,17 @@ static int enable_flash_ich(struct pci_dev *dev, char *name, int bios_cntl)
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return 0;
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}
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static int enable_flash_ich_4e(struct pci_dev *dev, char *name)
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static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
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{
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return enable_flash_ich(dev, name, 0x4e);
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}
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static int enable_flash_ich_dc(struct pci_dev *dev, char *name)
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static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
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{
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return enable_flash_ich(dev, name, 0xdc);
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}
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static int enable_flash_vt823x(struct pci_dev *dev, char *name)
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static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
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{
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uint8_t val;
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@ -194,7 +196,7 @@ static int enable_flash_vt823x(struct pci_dev *dev, char *name)
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return 0;
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}
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static int enable_flash_cs5530(struct pci_dev *dev, char *name)
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static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
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{
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uint8_t reg8;
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@ -224,7 +226,7 @@ static int enable_flash_cs5530(struct pci_dev *dev, char *name)
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return 0;
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}
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static int enable_flash_cs5536(struct pci_dev *dev, char *name)
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static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
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{
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int fd_msr;
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unsigned char buf[8];
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@ -233,15 +235,15 @@ static int enable_flash_cs5536(struct pci_dev *dev, char *name)
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/* Geode systems write protect the BIOS via RCONFs (cache
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* settings similar to MTRRs). To unlock, change MSR 0x1808
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* top byte to 0x22. Reading and writing to msr, however
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* requires instrucitons rdmsr/wrmsr, which are ring0 privileged
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* requires instructions rdmsr/wrmsr, which are ring0 privileged
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* instructions so only the kernel can do the read/write. This
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* function, therefore, requires that the msr kernel module be
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* loaded to access these instructions from user space using
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* device /dev/cpu/0/msr. This hard-coded driver location
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* could have potential problems on SMP machines since it
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* assumes cpu0, but it is safe on the geode which is not SMP.
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* assumes cpu0, but it is safe on the Geode which is not SMP.
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*
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* This is probably not portable beyond linux.
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* This is probably not portable beyond Linux.
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*/
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fd_msr = open("/dev/cpu/0/msr", O_RDONLY);
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@ -272,7 +274,7 @@ static int enable_flash_cs5536(struct pci_dev *dev, char *name)
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return 0;
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}
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static int enable_flash_sc1100(struct pci_dev *dev, char *name)
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static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
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{
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uint8_t new;
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@ -288,16 +290,14 @@ static int enable_flash_sc1100(struct pci_dev *dev, char *name)
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return 0;
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}
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||||
|
||||
static int enable_flash_sis5595(struct pci_dev *dev, char *name)
|
||||
static int enable_flash_sis5595(struct pci_dev *dev, const char *name)
|
||||
{
|
||||
uint8_t new, newer;
|
||||
|
||||
new = pci_read_byte(dev, 0x45);
|
||||
|
||||
/* clear bit 5 */
|
||||
new &= (~0x20);
|
||||
/* set bit 2 */
|
||||
new |= 0x4;
|
||||
new &= (~0x20); /* Clear bit 5. */
|
||||
new |= 0x4; /* Set bit 2. */
|
||||
|
||||
pci_write_byte(dev, 0x45, new);
|
||||
|
||||
|
|
@ -311,16 +311,11 @@ static int enable_flash_sis5595(struct pci_dev *dev, char *name)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int enable_flash_amd8111(struct pci_dev *dev, char *name)
|
||||
static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
|
||||
{
|
||||
/* register 4e.b gets or'ed with one */
|
||||
uint8_t old, new;
|
||||
|
||||
/* if it fails, it fails. There are so many variations of broken mobos
|
||||
* that it is hard to argue that we should quit at this point.
|
||||
*/
|
||||
|
||||
/* enable decoding at 0xffb00000 to 0xffffffff */
|
||||
/* Enable decoding at 0xffb00000 to 0xffffffff. */
|
||||
old = pci_read_byte(dev, 0x43);
|
||||
new = old | 0xC0;
|
||||
if (new != old) {
|
||||
|
|
@ -344,17 +339,10 @@ static int enable_flash_amd8111(struct pci_dev *dev, char *name)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int enable_flash_ck804(struct pci_dev *dev, char *name)
|
||||
static int enable_flash_ck804(struct pci_dev *dev, const char *name)
|
||||
{
|
||||
/* register 4e.b gets or'ed with one */
|
||||
uint8_t old, new;
|
||||
|
||||
/* if it fails, it fails. There are so many variations of broken mobos
|
||||
* that it is hard to argue that we should quit at this point.
|
||||
*/
|
||||
|
||||
/* dump_pci_device(dev); */
|
||||
|
||||
old = pci_read_byte(dev, 0x88);
|
||||
new = old | 0xc0;
|
||||
if (new != old) {
|
||||
|
|
@ -378,14 +366,14 @@ static int enable_flash_ck804(struct pci_dev *dev, char *name)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int enable_flash_sb400(struct pci_dev *dev, char *name)
|
||||
/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
|
||||
static int enable_flash_sb400(struct pci_dev *dev, const char *name)
|
||||
{
|
||||
uint8_t tmp;
|
||||
|
||||
struct pci_filter f;
|
||||
struct pci_dev *smbusdev;
|
||||
|
||||
/* then look for the smbus device */
|
||||
/* Look for the SMBus device. */
|
||||
pci_filter_init((struct pci_access *)0, &f);
|
||||
f.vendor = 0x1002;
|
||||
f.device = 0x4372;
|
||||
|
|
@ -397,21 +385,21 @@ static int enable_flash_sb400(struct pci_dev *dev, char *name)
|
|||
}
|
||||
|
||||
if (!smbusdev) {
|
||||
fprintf(stderr, "ERROR: SMBus device not found. aborting\n");
|
||||
fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
/* enable some smbus stuff */
|
||||
/* Enable some SMBus stuff. */
|
||||
tmp = pci_read_byte(smbusdev, 0x79);
|
||||
tmp |= 0x01;
|
||||
pci_write_byte(smbusdev, 0x79, tmp);
|
||||
|
||||
/* change southbridge */
|
||||
/* Change southbridge. */
|
||||
tmp = pci_read_byte(dev, 0x48);
|
||||
tmp |= 0x21;
|
||||
pci_write_byte(dev, 0x48, tmp);
|
||||
|
||||
/* now become a bit silly. */
|
||||
/* Now become a bit silly. */
|
||||
tmp = inb(0xc6f);
|
||||
outb(tmp, 0xeb);
|
||||
outb(tmp, 0xeb);
|
||||
|
|
@ -423,19 +411,12 @@ static int enable_flash_sb400(struct pci_dev *dev, char *name)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int enable_flash_mcp55(struct pci_dev *dev, char *name)
|
||||
static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
|
||||
{
|
||||
/* register 4e.b gets or'ed with one */
|
||||
unsigned char old, new, byte;
|
||||
unsigned short word;
|
||||
uint8_t old, new, byte;
|
||||
uint16_t word;
|
||||
|
||||
/* if it fails, it fails. There are so many variations of broken mobos
|
||||
* that it is hard to argue that we should quit at this point.
|
||||
*/
|
||||
|
||||
/* dump_pci_device(dev); */
|
||||
|
||||
/* Set the 0-16 MB enable bits */
|
||||
/* Set the 0-16 MB enable bits. */
|
||||
byte = pci_read_byte(dev, 0x88);
|
||||
byte |= 0xff; /* 256K */
|
||||
pci_write_byte(dev, 0x88, byte);
|
||||
|
|
@ -462,7 +443,7 @@ static int enable_flash_mcp55(struct pci_dev *dev, char *name)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int enable_flash_ht1000(struct pci_dev *dev, char *name)
|
||||
static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
|
||||
{
|
||||
uint8_t byte;
|
||||
|
||||
|
|
@ -479,12 +460,12 @@ static int enable_flash_ht1000(struct pci_dev *dev, char *name)
|
|||
}
|
||||
|
||||
typedef struct penable {
|
||||
unsigned short vendor, device;
|
||||
char *name;
|
||||
int (*doit) (struct pci_dev * dev, char *name);
|
||||
uint16_t vendor, device;
|
||||
const char *name;
|
||||
int (*doit) (struct pci_dev *dev, const char *name);
|
||||
} FLASH_ENABLE;
|
||||
|
||||
static FLASH_ENABLE enables[] = {
|
||||
static const FLASH_ENABLE enables[] = {
|
||||
{0x1039, 0x0630, "SIS630", enable_flash_sis630},
|
||||
{0x8086, 0x7110, "PIIX4/PIIX4E/PIIX4M", enable_flash_piix4},
|
||||
{0x8086, 0x7198, "Intel 440MX", enable_flash_piix4},
|
||||
|
|
@ -517,17 +498,14 @@ static FLASH_ENABLE enables[] = {
|
|||
{0x1022, 0x2080, "AMD GEODE CS5536", enable_flash_cs5536},
|
||||
{0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
|
||||
{0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533},
|
||||
/* this fallthrough looks broken. */
|
||||
{0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */
|
||||
{0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */
|
||||
{0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, /* Slave, should not be here, to fix known bug for A01. */
|
||||
|
||||
{0x10de, 0x0260, "NVidia MCP51", enable_flash_ck804},
|
||||
{0x10de, 0x0261, "NVidia MCP51", enable_flash_ck804},
|
||||
{0x10de, 0x0262, "NVidia MCP51", enable_flash_ck804},
|
||||
{0x10de, 0x0263, "NVidia MCP51", enable_flash_ck804},
|
||||
|
||||
{0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* Gigabyte m57sli-s4 */
|
||||
{0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* M57SLI-S4 */
|
||||
{0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
{0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
{0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
|
|
@ -535,19 +513,18 @@ static FLASH_ENABLE enables[] = {
|
|||
{0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
{0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
{0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */
|
||||
|
||||
{0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
|
||||
|
||||
{0x1002, 0x4377, "ATI SB400", enable_flash_sb400},
|
||||
{0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000},
|
||||
};
|
||||
|
||||
int chipset_flash_enable(void)
|
||||
{
|
||||
struct pci_dev *dev = 0;
|
||||
int ret = -2; /* nothing! */
|
||||
int ret = -2; /* Nothing! */
|
||||
int i;
|
||||
|
||||
/* now let's try to find the chipset we have ... */
|
||||
/* Now let's try to find the chipset we have... */
|
||||
/* TODO: Use ARRAY_SIZE. */
|
||||
for (i = 0; i < sizeof(enables) / sizeof(enables[0]); i++) {
|
||||
dev = pci_dev_find(enables[i].vendor, enables[i].device);
|
||||
if (dev)
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
#include <stdio.h>
|
||||
|
||||
struct flashchip {
|
||||
char *name;
|
||||
const char *name;
|
||||
int manufacture_id;
|
||||
int model_id;
|
||||
|
||||
|
|
@ -43,18 +43,18 @@ struct flashchip {
|
|||
int (*write) (struct flashchip *flash, uint8_t *buf);
|
||||
int (*read) (struct flashchip *flash, uint8_t *buf);
|
||||
|
||||
/* some flash devices have an additional
|
||||
* register space
|
||||
*/
|
||||
/* Some flash devices have an additional register space. */
|
||||
volatile uint8_t *virtual_memory;
|
||||
volatile uint8_t *virtual_registers;
|
||||
};
|
||||
|
||||
extern struct flashchip flashchips[];
|
||||
|
||||
/* Please keep this list sorted alphabetically by manufacturer. The first
|
||||
/*
|
||||
* Please keep this list sorted alphabetically by manufacturer. The first
|
||||
* entry of each section should be the manufacturer ID, followed by the
|
||||
* list of devices from that manufacturer (sorted by device IDs).
|
||||
*
|
||||
* All LPC/FWH parts (parallel flash) have 8-bit device IDs.
|
||||
* All SPI parts have 16-bit device IDs.
|
||||
*/
|
||||
|
|
@ -80,9 +80,11 @@ extern struct flashchip flashchips[];
|
|||
#define EMST_ID 0x8C /* EMST / EFST */
|
||||
#define EMST_F49B002UA 0x00
|
||||
|
||||
/*
|
||||
* EN25 chips are SPI, first byte of device ID is memory type,
|
||||
* second byte of device ID is log(bitsize)-9.
|
||||
*/
|
||||
#define EON_ID 0x1C /* EON */
|
||||
/* EN25 chips are SPI, first byte of device id is memory type,
|
||||
* second byte of device id is log(bitsize)-9. */
|
||||
#define EN_25B05 0x2010 /* 2^19 kbit or 2^16 kByte */
|
||||
#define EN_25B10 0x2011
|
||||
#define EN_25B20 0x2012
|
||||
|
|
@ -103,13 +105,15 @@ extern struct flashchip flashchips[];
|
|||
#define ISSI_ID 0xD5 /* ISSI */
|
||||
|
||||
#define MSYSTEMS_ID 0x156F /* M-Systems */
|
||||
#define MSYSTEMS_MD2200 0xDB /* ? */
|
||||
#define MSYSTEMS_MD2200 0xDB
|
||||
#define MSYSTEMS_MD2800 0x30 /* hmm -- both 0x30 */
|
||||
#define MSYSTEMS_MD2802 0x30 /* hmm -- both 0x30 */
|
||||
|
||||
/*
|
||||
* MX25 chips are SPI, first byte of device ID is memory type,
|
||||
* second byte of device ID is log(bitsize)-9.
|
||||
*/
|
||||
#define MX_ID 0xC2 /* Macronix (MX) */
|
||||
/* MX25 chips are SPI, first byte of device id is memory type,
|
||||
* second byte of device id is log(bitsize)-9. */
|
||||
#define MX_25L512 0x2010 /* 2^19 kbit or 2^16 kByte */
|
||||
#define MX_25L1005 0x2011
|
||||
#define MX_25L2005 0x2012
|
||||
|
|
@ -129,9 +133,11 @@ extern struct flashchip flashchips[];
|
|||
#define SHARP_ID 0xB0 /* Sharp */
|
||||
#define SHARP_LHF00L04 0xCF
|
||||
|
||||
/*
|
||||
* SST25 chips are SPI, first byte of device ID is memory type, second
|
||||
* byte of device ID is related to log(bitsize) at least for some chips.
|
||||
*/
|
||||
#define SST_ID 0xBF /* SST */
|
||||
/* SST25 chips are SPI, first byte of device id is memory type, second
|
||||
* byte of device id is related to log(bitsize) at least for some chips. */
|
||||
#define SST_25WF512 0x2501
|
||||
#define SST_25WF010 0x2502
|
||||
#define SST_25WF020 0x2503
|
||||
|
|
@ -196,22 +202,23 @@ extern struct flashchip flashchips[];
|
|||
#define W_49V002A 0xB0
|
||||
#define W_49V002FA 0x32
|
||||
|
||||
/* function prototypes from udelay.h */
|
||||
|
||||
/* udelay.c */
|
||||
void myusec_delay(int time);
|
||||
void myusec_calibrate_delay();
|
||||
|
||||
/* pci handling for board/chipset_enable */
|
||||
struct pci_access *pacc; /* For board and chipset_enable */
|
||||
/* PCI handling for board/chipset_enable */
|
||||
struct pci_access *pacc;
|
||||
struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
|
||||
struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
|
||||
uint16_t card_vendor, uint16_t card_device);
|
||||
|
||||
int board_flash_enable(char *vendor, char *part); /* board_enable.c */
|
||||
int chipset_flash_enable(void); /* chipset_enable.c */
|
||||
/* board_enable.c */
|
||||
int board_flash_enable(const char *vendor, const char *part);
|
||||
|
||||
/* physical memory mapping device */
|
||||
/* chipset_enable.c */
|
||||
int chipset_flash_enable(void);
|
||||
|
||||
/* Physical memory mapping device */
|
||||
#if defined (__sun) && (defined(__i386) || defined(__amd64))
|
||||
# define MEM_DEV "/dev/xsvc"
|
||||
#else
|
||||
|
|
|
|||
Loading…
Reference in New Issue