AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT
Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17534 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Kyösti Mälkki
parent
cc37bbd7ac
commit
187543c90d
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@ -16,6 +16,7 @@
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config CPU_AMD_PI_00630F01
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bool
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select PCI_IO_CFG_EXT
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select MMCONF_SUPPORT_DEFAULT
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select X86_AMD_FIXED_MTRRS
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if CPU_AMD_PI_00630F01
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@ -16,6 +16,7 @@
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config CPU_AMD_PI_00660F01
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bool
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select PCI_IO_CFG_EXT
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select MMCONF_SUPPORT_DEFAULT
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select X86_AMD_FIXED_MTRRS
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if CPU_AMD_PI_00660F01
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@ -16,6 +16,7 @@
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config CPU_AMD_PI_00670F00
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bool
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select PCI_IO_CFG_EXT
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select MMCONF_SUPPORT_DEFAULT
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select X86_AMD_FIXED_MTRRS
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if CPU_AMD_PI_00670F00
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@ -16,6 +16,7 @@
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config CPU_AMD_PI_00730F01
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bool
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select PCI_IO_CFG_EXT
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select MMCONF_SUPPORT_DEFAULT
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select X86_AMD_FIXED_MTRRS
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if CPU_AMD_PI_00730F01
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@ -32,6 +32,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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void *resume_backup_memory;
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#endif
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/* Must come first to enable PCI MMCONF. */
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amd_initmmio();
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hudson_lpc_port80();
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@ -37,6 +37,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* Must come first to enable PCI MMCONF. */
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amd_initmmio();
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/*
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* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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* LpcClk[1:0]". This following register setting has been
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@ -48,8 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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outb(0xD2, 0xcd6);
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outb(0x00, 0xcd7);
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amd_initmmio();
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hudson_lpc_port80();
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if (!cpu_init_detectedx && boot_cpu()) {
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@ -41,6 +41,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* Must come first to enable PCI MMCONF. */
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amd_initmmio();
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/*
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* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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* LpcClk[1:0]". This following register setting has been
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@ -52,7 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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outb(0xD2, 0xcd6);
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outb(0x00, 0xcd7);
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amd_initmmio();
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hudson_lpc_decode();
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outb(0x24, 0xCD6);
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@ -37,6 +37,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* Must come first to enable PCI MMCONF. */
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amd_initmmio();
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/*
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* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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* LpcClk[1:0]". This following register setting has been
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@ -48,8 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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outb(0xD2, 0xcd6);
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outb(0x00, 0xcd7);
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amd_initmmio();
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hudson_lpc_port80();
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if (!cpu_init_detectedx && boot_cpu()) {
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@ -41,6 +41,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* Must come first to enable PCI MMCONF. */
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amd_initmmio();
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/*
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* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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* LpcClk[1:0]". This following register setting has been
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@ -52,8 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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outb(0xD2, 0xcd6);
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outb(0x00, 0xcd7);
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amd_initmmio();
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hudson_lpc_port80();
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if (!cpu_init_detectedx && boot_cpu()) {
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@ -14,7 +14,6 @@
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##
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config NORTHBRIDGE_AMD_PI_00630F01
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bool
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select MMCONF_SUPPORT
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if NORTHBRIDGE_AMD_PI_00630F01
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@ -14,7 +14,6 @@
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##
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config NORTHBRIDGE_AMD_PI_00660F01
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bool
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select MMCONF_SUPPORT
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if NORTHBRIDGE_AMD_PI_00660F01
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@ -14,7 +14,6 @@
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##
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config NORTHBRIDGE_AMD_PI_00670F00
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bool
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select MMCONF_SUPPORT
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if NORTHBRIDGE_AMD_PI_00670F00
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@ -15,7 +15,6 @@
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##
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config NORTHBRIDGE_AMD_PI_00730F01
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bool
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select MMCONF_SUPPORT
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if NORTHBRIDGE_AMD_PI_00730F01
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