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AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT 

Vendorcode always does PCI MMCONF access once it is
enabled via MSR.

In coreboot proper, we don't give opportunity to make
pci_read/write calls before PCI MMCONF is enabled via MSR.
This happens early in romstage amd_initmmio() for all cores.

Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17534
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-11-20 11:03:13 +02:00
parent cc37bbd7ac
commit 187543c90d
13 changed files with 17 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/cpu/amd/pi/00630F01/Kconfig
View File

@ -16,6 +16,7 @@
config CPU_AMD_PI_00630F01 config CPU_AMD_PI_00630F01
bool bool
select PCI_IO_CFG_EXT select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS select X86_AMD_FIXED_MTRRS
if CPU_AMD_PI_00630F01 if CPU_AMD_PI_00630F01

1
src/cpu/amd/pi/00660F01/Kconfig
View File

@ -16,6 +16,7 @@
config CPU_AMD_PI_00660F01 config CPU_AMD_PI_00660F01
bool bool
select PCI_IO_CFG_EXT select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS select X86_AMD_FIXED_MTRRS
if CPU_AMD_PI_00660F01 if CPU_AMD_PI_00660F01

1
src/cpu/amd/pi/00670F00/Kconfig
View File

@ -16,6 +16,7 @@
config CPU_AMD_PI_00670F00 config CPU_AMD_PI_00670F00
bool bool
select PCI_IO_CFG_EXT select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS select X86_AMD_FIXED_MTRRS
if CPU_AMD_PI_00670F00 if CPU_AMD_PI_00670F00

1
src/cpu/amd/pi/00730F01/Kconfig
View File

@ -16,6 +16,7 @@
config CPU_AMD_PI_00730F01 config CPU_AMD_PI_00730F01
bool bool
select PCI_IO_CFG_EXT select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS select X86_AMD_FIXED_MTRRS
if CPU_AMD_PI_00730F01 if CPU_AMD_PI_00730F01

1
src/mainboard/amd/bettong/romstage.c
View File

@ -32,6 +32,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void *resume_backup_memory; void *resume_backup_memory;
#endif #endif
/* Must come first to enable PCI MMCONF. */
amd_initmmio(); amd_initmmio();
hudson_lpc_port80(); hudson_lpc_port80();

5
src/mainboard/amd/db-ft3b-lc/romstage.c
View File

@ -37,6 +37,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
u32 val; u32 val;
/* Must come first to enable PCI MMCONF. */
amd_initmmio();
/* /*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". This following register setting has been * LpcClk[1:0]". This following register setting has been
@ -48,8 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6); outb(0xD2, 0xcd6);
outb(0x00, 0xcd7); outb(0x00, 0xcd7);
amd_initmmio();
hudson_lpc_port80(); hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) { if (!cpu_init_detectedx && boot_cpu()) {

4
src/mainboard/amd/lamar/romstage.c
View File

@ -41,6 +41,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
u32 val; u32 val;
/* Must come first to enable PCI MMCONF. */
amd_initmmio();
/* /*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". This following register setting has been * LpcClk[1:0]". This following register setting has been
@ -52,7 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6); outb(0xD2, 0xcd6);
outb(0x00, 0xcd7); outb(0x00, 0xcd7);
amd_initmmio();
hudson_lpc_decode(); hudson_lpc_decode();
outb(0x24, 0xCD6); outb(0x24, 0xCD6);

5
src/mainboard/amd/olivehillplus/romstage.c
View File

@ -37,6 +37,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
u32 val; u32 val;
/* Must come first to enable PCI MMCONF. */
amd_initmmio();
/* /*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". This following register setting has been * LpcClk[1:0]". This following register setting has been
@ -48,8 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6); outb(0xD2, 0xcd6);
outb(0x00, 0xcd7); outb(0x00, 0xcd7);
amd_initmmio();
hudson_lpc_port80(); hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) { if (!cpu_init_detectedx && boot_cpu()) {

5
src/mainboard/bap/ode_e21XX/romstage.c
View File

@ -41,6 +41,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
u32 val; u32 val;
/* Must come first to enable PCI MMCONF. */
amd_initmmio();
/* /*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". This following register setting has been * LpcClk[1:0]". This following register setting has been
@ -52,8 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6); outb(0xD2, 0xcd6);
outb(0x00, 0xcd7); outb(0x00, 0xcd7);
amd_initmmio();
hudson_lpc_port80(); hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) { if (!cpu_init_detectedx && boot_cpu()) {

1
src/northbridge/amd/pi/00630F01/Kconfig
View File

@ -14,7 +14,6 @@
## ##
config NORTHBRIDGE_AMD_PI_00630F01 config NORTHBRIDGE_AMD_PI_00630F01
bool bool
select MMCONF_SUPPORT
if NORTHBRIDGE_AMD_PI_00630F01 if NORTHBRIDGE_AMD_PI_00630F01

1
src/northbridge/amd/pi/00660F01/Kconfig
View File

@ -14,7 +14,6 @@
## ##
config NORTHBRIDGE_AMD_PI_00660F01 config NORTHBRIDGE_AMD_PI_00660F01
bool bool
select MMCONF_SUPPORT
if NORTHBRIDGE_AMD_PI_00660F01 if NORTHBRIDGE_AMD_PI_00660F01

1
src/northbridge/amd/pi/00670F00/Kconfig
View File

@ -14,7 +14,6 @@
## ##
config NORTHBRIDGE_AMD_PI_00670F00 config NORTHBRIDGE_AMD_PI_00670F00
bool bool
select MMCONF_SUPPORT
if NORTHBRIDGE_AMD_PI_00670F00 if NORTHBRIDGE_AMD_PI_00670F00

1
src/northbridge/amd/pi/00730F01/Kconfig
View File

@ -15,7 +15,6 @@
## ##
config NORTHBRIDGE_AMD_PI_00730F01 config NORTHBRIDGE_AMD_PI_00730F01
bool bool
select MMCONF_SUPPORT
if NORTHBRIDGE_AMD_PI_00730F01 if NORTHBRIDGE_AMD_PI_00730F01