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soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblock 

This change adds a call to gspi_early_bar_init in bootblock to
allocate a temporary BAR for any GSPI buses that are accessed before
resource allocation is done in ramstage.

Change-Id: I82387a76d20fb272da6271dd9e5bf2c835d5b146
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22781
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh 2017-12-07 18:39:34 -08:00 committed by Furquan Shaikh
parent 044dfe9b69
commit 1876f3ae45
1 changed files with 2 additions and 0 deletions
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2
src/soc/intel/cannonlake/bootblock/pch.c
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@ -16,6 +16,7 @@
#include <device/device.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/gspi.h>
#include <intelblocks/pcr.h>
#include <intelblocks/rtc.h>
#include <intelblocks/pmclib.h>
@ -98,6 +99,7 @@ static void soc_config_pwrmbase(void)
void bootblock_pch_early_init(void)
{
fast_spi_early_init(SPI_BASE_ADDRESS);
gspi_early_bar_init();
enable_p2sbbar();
/*
* Enabling PWRM Base for accessing