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soc/amd/picasso: split southbridge into bootblock and ramstage code 

The ramstage parts gets renamed to fch.c and the bootblock one to
early_fch.c. No functionality from the old southbridge file is used in
romstage, so don't link it there.

Change-Id: I7ca3b5238c3b841191dd0459996b691edd76fbf8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2020-12-08 02:25:05 +01:00
parent 64de2c151d
commit 187f59accb
3 changed files with 61 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/soc/amd/picasso/Makefile.inc
View File

@ -13,7 +13,7 @@ all-y += config.c
bootblock-y += bootblock.c
bootblock-y += aoac.c
bootblock-y += southbridge.c
bootblock-y += early_fch.c
bootblock-y += i2c.c
bootblock-y += uart.c
bootblock-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
@ -28,7 +28,6 @@ romstage-y += memmap.c
romstage-y += uart.c
romstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
romstage-y += aoac.c
romstage-y += southbridge.c
romstage-y += psp.c
romstage-y += mrc_cache.c
@ -49,7 +48,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c
ramstage-y += gpio.c
ramstage-y += aoac.c
ramstage-y += southbridge.c
ramstage-y += fch.c
ramstage-y += reset.c
ramstage-y += acp.c
ramstage-y += sata.c

59
src/soc/amd/picasso/early_fch.c Normal file
View File

@ -0,0 +1,59 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/acpimmio.h>
#include <amdblocks/espi.h>
#include <amdblocks/lpc.h>
#include <amdblocks/smbus.h>
#include <amdblocks/spi.h>
#include <console/console.h>
#include <soc/i2c.h>
#include <soc/southbridge.h>
#include <soc/uart.h>
#include <types.h>
static void lpc_configure_decodes(void)
{
if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))
lpc_enable_port80();
}
/* Before console init */
void fch_pre_init(void)
{
lpc_early_init();
if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
lpc_configure_decodes();
fch_spi_early_init();
enable_acpimmio_decode_pm04();
fch_smbus_init();
fch_enable_cf9_io();
fch_enable_legacy_io();
enable_aoac_devices();
sb_reset_i2c_slaves();
/*
* On reset Range_0 defaults to enabled. We want to start with a clean
* slate to not have things unexpectedly enabled.
*/
clear_uart_legacy_config();
if (CONFIG(PICASSO_CONSOLE_UART))
set_uart_config(CONFIG_UART_FOR_CONSOLE);
}
/* After console init */
void fch_early_init(void)
{
fch_print_pmxc0_status();
i2c_soc_early_init();
if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
lpc_disable_spi_rom_sharing();
if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
espi_setup();
espi_configure_decodes();
}
}

52
src/soc/amd/picasso/southbridge.c → src/soc/amd/picasso/fch.c
View File

@ -14,18 +14,13 @@
#include <amdblocks/amd_pci_util.h>
#include <amdblocks/reset.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/espi.h>
#include <amdblocks/lpc.h>
#include <amdblocks/acpi.h>
#include <amdblocks/smbus.h>
#include <amdblocks/spi.h>
#include <amdblocks/smi.h>
#include <soc/acpi.h>
#include <soc/cpu.h>
#include <soc/i2c.h>
#include <soc/southbridge.h>
#include <soc/smi.h>
#include <soc/uart.h>
#include <soc/amd_pci_int_defs.h>
#include <soc/pci_devs.h>
#include <soc/nvs.h>
@ -100,53 +95,6 @@ void sb_clk_output_48Mhz(void)
misc_write32(MISC_CLK_CNTL1, ctrl);
}
static void lpc_configure_decodes(void)
{
if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))
lpc_enable_port80();
}
/* Before console init */
void fch_pre_init(void)
{
lpc_early_init();
if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
lpc_configure_decodes();
fch_spi_early_init();
enable_acpimmio_decode_pm04();
fch_smbus_init();
fch_enable_cf9_io();
fch_enable_legacy_io();
enable_aoac_devices();
sb_reset_i2c_slaves();
/*
* On reset Range_0 defaults to enabled. We want to start with a clean
* slate to not have things unexpectedly enabled.
*/
clear_uart_legacy_config();
if (CONFIG(PICASSO_CONSOLE_UART))
set_uart_config(CONFIG_UART_FOR_CONSOLE);
}
/* After console init */
void fch_early_init(void)
{
fch_print_pmxc0_status();
i2c_soc_early_init();
if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
lpc_disable_spi_rom_sharing();
if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
espi_setup();
espi_configure_decodes();
}
}
void sb_enable(struct device *dev)
{
printk(BIOS_DEBUG, "%s\n", __func__);