soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macros
To have both the PCI function number and the register offset into the config space of that function of the data fabric device in the data fabric register definitions, introduce and use the DF_REG_ID, DF_REG_FN and DF_REG_REG macros. The DF_REG_ID macro is used for register definitions where both the function number and the register offset are specified, and the DF_REG_FN and DF_REG_REG macros are used to extract the function number and the register offset from the register defines. This will allow having one define for accessing an indexed group of registers that are on different functions of the data fabric device. TEST=MMIO resources read from the data fabric's MMIO decode registers don't change on Mandolin and the ACPI CRAT table is also identical. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I63a284b26081c170a217b082b100c482f6158e7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/76886 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Felix Held
parent
8677d2ddb8
commit
18a3c230ff
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@ -3,20 +3,21 @@
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#ifndef AMD_CEZANNE_DATA_FABRIC_H
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#define AMD_CEZANNE_DATA_FABRIC_H
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#include <amdblocks/data_fabric_defs.h>
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#include <types.h>
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/* D18F0 - Fabric Configuration registers */
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#define D18F0_MMIO_BASE0 0x200
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#define D18F0_MMIO_LIMIT0 0x204
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#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0x200)
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#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0x204)
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#define D18F0_MMIO_SHIFT 16
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#define D18F0_MMIO_CTRL0 0x208
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#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0x208)
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#define DF_MMIO_REG_SET_SIZE 4
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#define DF_MMIO_REG_SET_COUNT 8
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#define DF_FICAA_BIOS 0x5C
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#define DF_FICAD_LO 0x98
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#define DF_FICAD_HI 0x9C
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#define DF_FICAA_BIOS DF_REG_ID(4, 0x5C)
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#define DF_FICAD_LO DF_REG_ID(4, 0x98)
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#define DF_FICAD_HI DF_REG_ID(4, 0x9C)
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#define IOMS0_FABRIC_ID 10
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@ -11,38 +11,41 @@
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#include <soc/pci_devs.h>
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#include <types.h>
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static void data_fabric_set_indirect_address(uint8_t func, uint16_t reg, uint8_t instance_id)
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static void data_fabric_set_indirect_address(uint16_t fn_reg, uint8_t instance_id)
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{
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union df_ficaa ficaa = { .cfg_inst_acc_en = 1 }; /* target only specific instance */
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/* convert register address to 32-bit register number */
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ficaa.reg_num = reg >> 2;
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ficaa.func_num = func;
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ficaa.reg_num = DF_REG_OFFSET(fn_reg) >> 2;
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ficaa.func_num = DF_REG_FN(fn_reg);
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ficaa.inst_id = instance_id;
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pci_write_config32(SOC_DF_F4_DEV, DF_FICAA_BIOS, ficaa.raw);
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pci_write_config32(_SOC_DEV(DF_DEV, DF_REG_FN(DF_FICAA_BIOS)),
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DF_REG_OFFSET(DF_FICAA_BIOS), ficaa.raw);
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}
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uint32_t data_fabric_read32(uint8_t function, uint16_t reg, uint8_t instance_id)
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uint32_t data_fabric_read32(uint16_t fn_reg, uint8_t instance_id)
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{
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/* Broadcast reads might return unexpected results when a register has different
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contents in the different instances. */
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if (instance_id == BROADCAST_FABRIC_ID)
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return data_fabric_broadcast_read32(function, reg);
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return data_fabric_broadcast_read32(fn_reg);
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/* non-broadcast data fabric accesses need to be done via indirect access */
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data_fabric_set_indirect_address(function, reg, instance_id);
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return pci_read_config32(SOC_DF_F4_DEV, DF_FICAD_LO);
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data_fabric_set_indirect_address(fn_reg, instance_id);
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return pci_read_config32(_SOC_DEV(DF_DEV, DF_REG_FN(DF_FICAD_LO)),
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DF_REG_OFFSET(DF_FICAD_LO));
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}
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void data_fabric_write32(uint8_t function, uint16_t reg, uint8_t instance_id, uint32_t data)
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void data_fabric_write32(uint16_t fn_reg, uint8_t instance_id, uint32_t data)
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{
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if (instance_id == BROADCAST_FABRIC_ID) {
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data_fabric_broadcast_write32(function, reg, data);
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data_fabric_broadcast_write32(fn_reg, data);
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return;
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}
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/* non-broadcast data fabric accesses need to be done via indirect access */
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data_fabric_set_indirect_address(function, reg, instance_id);
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pci_write_config32(SOC_DF_F4_DEV, DF_FICAD_LO, data);
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data_fabric_set_indirect_address(fn_reg, instance_id);
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pci_write_config32(_SOC_DEV(DF_DEV, DF_REG_FN(DF_FICAD_LO)),
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DF_REG_OFFSET(DF_FICAD_LO), data);
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}
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void data_fabric_print_mmio_conf(void)
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@ -53,12 +56,12 @@ void data_fabric_print_mmio_conf(void)
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"=== Data Fabric MMIO configuration registers ===\n"
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"idx base limit control R W NP F-ID\n");
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for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) {
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control.raw = data_fabric_broadcast_read32(0, DF_MMIO_CONTROL(i));
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control.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(i));
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/* Base and limit address registers don't contain the lower address bits, but
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are shifted by D18F0_MMIO_SHIFT bits */
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base = (uint64_t)data_fabric_broadcast_read32(0, DF_MMIO_BASE(i))
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base = (uint64_t)data_fabric_broadcast_read32(DF_MMIO_BASE(i))
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<< D18F0_MMIO_SHIFT;
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limit = (uint64_t)data_fabric_broadcast_read32(0, DF_MMIO_LIMIT(i))
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limit = (uint64_t)data_fabric_broadcast_read32(DF_MMIO_LIMIT(i))
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<< D18F0_MMIO_SHIFT;
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/* Lower D18F0_MMIO_SHIFT address limit bits are all 1 */
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limit += (1 << D18F0_MMIO_SHIFT) - 1;
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@ -74,15 +77,15 @@ void data_fabric_print_mmio_conf(void)
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void data_fabric_disable_mmio_reg(unsigned int reg)
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{
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union df_mmio_control ctrl = { .fabric_id = IOMS0_FABRIC_ID };
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data_fabric_broadcast_write32(0, DF_MMIO_CONTROL(reg), ctrl.raw);
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data_fabric_broadcast_write32(0, DF_MMIO_BASE(reg), 0);
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data_fabric_broadcast_write32(0, DF_MMIO_LIMIT(reg), 0);
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data_fabric_broadcast_write32(DF_MMIO_CONTROL(reg), ctrl.raw);
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data_fabric_broadcast_write32(DF_MMIO_BASE(reg), 0);
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data_fabric_broadcast_write32(DF_MMIO_LIMIT(reg), 0);
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}
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static bool is_mmio_reg_disabled(unsigned int reg)
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{
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union df_mmio_control ctrl;
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ctrl.raw = data_fabric_broadcast_read32(0, DF_MMIO_CONTROL(reg));
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ctrl.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(reg));
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return !(ctrl.we || ctrl.re);
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}
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@ -128,12 +131,12 @@ void data_fabric_set_mmio_np(void)
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for (i = 0; i < DF_MMIO_REG_SET_COUNT; i++) {
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/* Adjust all registers that overlap */
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ctrl.raw = data_fabric_broadcast_read32(0, DF_MMIO_CONTROL(i));
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ctrl.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(i));
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if (!(ctrl.we || ctrl.re))
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continue; /* not enabled */
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base = data_fabric_broadcast_read32(0, DF_MMIO_BASE(i));
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limit = data_fabric_broadcast_read32(0, DF_MMIO_LIMIT(i));
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base = data_fabric_broadcast_read32(DF_MMIO_BASE(i));
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limit = data_fabric_broadcast_read32(DF_MMIO_LIMIT(i));
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if (base > np_top || limit < np_bot)
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continue; /* no overlap at all */
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@ -145,7 +148,7 @@ void data_fabric_set_mmio_np(void)
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if (base < np_bot && limit > np_top) {
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/* Split the configured region */
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data_fabric_broadcast_write32(0, DF_MMIO_LIMIT(i), np_bot - 1);
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data_fabric_broadcast_write32(DF_MMIO_LIMIT(i), np_bot - 1);
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reg = data_fabric_find_unused_mmio_reg();
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if (reg < 0) {
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/* Although a pair could be freed later, this condition is
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@ -154,17 +157,17 @@ void data_fabric_set_mmio_np(void)
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printk(BIOS_ERR, "Not enough NB MMIO routing registers\n");
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continue;
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}
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data_fabric_broadcast_write32(0, DF_MMIO_BASE(reg), np_top + 1);
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data_fabric_broadcast_write32(0, DF_MMIO_LIMIT(reg), limit);
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data_fabric_broadcast_write32(0, DF_MMIO_CONTROL(reg), ctrl.raw);
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data_fabric_broadcast_write32(DF_MMIO_BASE(reg), np_top + 1);
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data_fabric_broadcast_write32(DF_MMIO_LIMIT(reg), limit);
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data_fabric_broadcast_write32(DF_MMIO_CONTROL(reg), ctrl.raw);
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continue;
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}
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/* If still here, adjust only the base or limit */
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if (base <= np_bot)
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data_fabric_broadcast_write32(0, DF_MMIO_LIMIT(i), np_bot - 1);
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data_fabric_broadcast_write32(DF_MMIO_LIMIT(i), np_bot - 1);
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else
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data_fabric_broadcast_write32(0, DF_MMIO_BASE(i), np_top + 1);
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data_fabric_broadcast_write32(DF_MMIO_BASE(i), np_top + 1);
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}
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reg = data_fabric_find_unused_mmio_reg();
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@ -175,9 +178,9 @@ void data_fabric_set_mmio_np(void)
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union df_mmio_control np_ctrl = { .fabric_id = IOMS0_FABRIC_ID,
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.np = 1, .we = 1, .re = 1 };
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data_fabric_broadcast_write32(0, DF_MMIO_BASE(reg), np_bot);
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data_fabric_broadcast_write32(0, DF_MMIO_LIMIT(reg), np_top);
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data_fabric_broadcast_write32(0, DF_MMIO_CONTROL(reg), np_ctrl.raw);
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data_fabric_broadcast_write32(DF_MMIO_BASE(reg), np_bot);
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data_fabric_broadcast_write32(DF_MMIO_LIMIT(reg), np_top);
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data_fabric_broadcast_write32(DF_MMIO_CONTROL(reg), np_ctrl.raw);
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data_fabric_print_mmio_conf();
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}
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@ -38,8 +38,8 @@ void amd_pci_domain_scan_bus(struct device *domain)
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static void data_fabric_get_mmio_base_size(unsigned int reg,
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resource_t *mmio_base, resource_t *mmio_limit)
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{
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const uint32_t base_reg = data_fabric_broadcast_read32(0, DF_MMIO_BASE(reg));
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const uint32_t limit_reg = data_fabric_broadcast_read32(0, DF_MMIO_LIMIT(reg));
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const uint32_t base_reg = data_fabric_broadcast_read32(DF_MMIO_BASE(reg));
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const uint32_t limit_reg = data_fabric_broadcast_read32(DF_MMIO_LIMIT(reg));
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/* The raw register values are bits 47..16 of the actual address */
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*mmio_base = (resource_t)base_reg << D18F0_MMIO_SHIFT;
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*mmio_limit = (((resource_t)limit_reg + 1) << D18F0_MMIO_SHIFT) - 1;
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@ -101,7 +101,7 @@ static void add_data_fabric_mmio_regions(struct device *domain, unsigned int *id
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(1ULL << get_usable_physical_address_bits()) - DF_RESERVED_TOP_12GB_MMIO_SIZE;
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for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) {
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ctrl.raw = data_fabric_broadcast_read32(0, DF_MMIO_CONTROL(i));
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ctrl.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(i));
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/* Relevant MMIO regions need to have both reads and writes enabled */
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if (!ctrl.we || !ctrl.re)
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@ -3,6 +3,7 @@
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#ifndef AMD_BLOCK_DATA_FABRIC_H
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#define AMD_BLOCK_DATA_FABRIC_H
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#include <amdblocks/data_fabric_defs.h>
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#include <amdblocks/pci_devs.h>
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#include <device/pci_ops.h>
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#include <soc/data_fabric.h>
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/* Last 12GB of the usable address space are reserved */
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#define DF_RESERVED_TOP_12GB_MMIO_SIZE (12ULL * GiB)
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uint32_t data_fabric_read32(uint8_t function, uint16_t reg, uint8_t instance_id);
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void data_fabric_write32(uint8_t function, uint16_t reg, uint8_t instance_id, uint32_t data);
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uint32_t data_fabric_read32(uint16_t fn_reg, uint8_t instance_id);
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void data_fabric_write32(uint16_t fn_reg, uint8_t instance_id, uint32_t data);
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static __always_inline
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uint32_t data_fabric_broadcast_read32(uint8_t function, uint16_t reg)
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uint32_t data_fabric_broadcast_read32(uint16_t fn_reg)
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{
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/* No bit masking required. Macros will apply mask to values. */
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return pci_read_config32(_SOC_DEV(DF_DEV, function), reg);
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return pci_read_config32(_SOC_DEV(DF_DEV, DF_REG_FN(fn_reg)), DF_REG_OFFSET(fn_reg));
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}
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static __always_inline
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void data_fabric_broadcast_write32(uint8_t function, uint16_t reg, uint32_t data)
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void data_fabric_broadcast_write32(uint16_t fn_reg, uint32_t data)
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{
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/* No bit masking required. Macros will apply mask to values. */
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pci_write_config32(_SOC_DEV(DF_DEV, function), reg, data);
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pci_write_config32(_SOC_DEV(DF_DEV, DF_REG_FN(fn_reg)), DF_REG_OFFSET(fn_reg), data);
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}
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void data_fabric_print_mmio_conf(void);
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@ -0,0 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef AMD_BLOCK_DATA_FABRIC_DEFS_H
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#define AMD_BLOCK_DATA_FABRIC_DEFS_H
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#define DF_REG_ID(fn, reg) (((fn) & 0x7) << 12 | ((reg) & 0xfff))
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#define DF_REG_FN(id) ((id) >> 12)
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#define DF_REG_OFFSET(id) ((id) & 0xfff)
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#endif /* AMD_BLOCK_DATA_FABRIC_DEFS_H */
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#ifndef AMD_GLINDA_DATA_FABRIC_H
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#define AMD_GLINDA_DATA_FABRIC_H
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#include <amdblocks/data_fabric_defs.h>
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#include <types.h>
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/* D18F0 - Fabric Configuration registers */
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#define D18F0_MMIO_BASE0 0xD80
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#define D18F0_MMIO_LIMIT0 0xD84
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#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0xD80)
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#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0xD84)
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#define D18F0_MMIO_SHIFT 16
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#define D18F0_MMIO_CTRL0 0xD88
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#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0xD88)
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#define DF_MMIO_REG_SET_SIZE 4
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#define DF_MMIO_REG_SET_COUNT 8
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#define DF_FICAA_BIOS 0x8C
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#define DF_FICAD_LO 0xB8
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#define DF_FICAD_HI 0xBC
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#define DF_FICAA_BIOS DF_REG_ID(4, 0x8C)
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#define DF_FICAD_LO DF_REG_ID(4, 0xB8)
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#define DF_FICAD_HI DF_REG_ID(4, 0xBC)
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#define IOMS0_FABRIC_ID 15
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@ -3,13 +3,14 @@
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#ifndef AMD_MENDOCINO_DATA_FABRIC_H
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#define AMD_MENDOCINO_DATA_FABRIC_H
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#include <amdblocks/data_fabric_defs.h>
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#include <types.h>
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/* D18F0 - Fabric Configuration registers */
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#define D18F0_MMIO_BASE0 0x200
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#define D18F0_MMIO_LIMIT0 0x204
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#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0x200)
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#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0x204)
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#define D18F0_MMIO_SHIFT 16
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#define D18F0_MMIO_CTRL0 0x208
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#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0x208)
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#if CONFIG(SOC_AMD_REMBRANDT)
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#define DF_MMIO_REG_SET_SIZE 3
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@ -19,9 +20,9 @@
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#define DF_MMIO_REG_SET_COUNT 8
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#define DF_FICAA_BIOS 0x5C
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#define DF_FICAD_LO 0x98
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#define DF_FICAD_HI 0x9C
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#define DF_FICAA_BIOS DF_REG_ID(4, 0x5C)
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#define DF_FICAD_LO DF_REG_ID(4, 0x98)
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#define DF_FICAD_HI DF_REG_ID(4, 0x9C)
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#define IOMS0_FABRIC_ID 9
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@ -3,20 +3,21 @@
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#ifndef AMD_PHOENIX_DATA_FABRIC_H
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#define AMD_PHOENIX_DATA_FABRIC_H
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#include <amdblocks/data_fabric_defs.h>
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#include <types.h>
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/* D18F0 - Fabric Configuration registers */
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#define D18F0_MMIO_BASE0 0xD80
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#define D18F0_MMIO_LIMIT0 0xD84
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#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0xD80)
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#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0xD84)
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#define D18F0_MMIO_SHIFT 16
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#define D18F0_MMIO_CTRL0 0xD88
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#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0xD88)
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#define DF_MMIO_REG_SET_SIZE 4
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#define DF_MMIO_REG_SET_COUNT 8
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#define DF_FICAA_BIOS 0x8C
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#define DF_FICAD_LO 0xB8
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#define DF_FICAD_HI 0xBC
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#define DF_FICAA_BIOS DF_REG_ID(4, 0x8C)
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#define DF_FICAD_LO DF_REG_ID(4, 0xB8)
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#define DF_FICAD_HI DF_REG_ID(4, 0xBC)
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#define IOMS0_FABRIC_ID 0x13
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||||
|
|
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|||
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@ -64,10 +64,10 @@ static unsigned long gen_crat_memory_entries(struct acpi_crat_header *crat,
|
|||
for (size_t dram_map_idx = 0; dram_map_idx < PICASSO_NUM_DRAM_REG;
|
||||
dram_map_idx++) {
|
||||
dram_base_reg =
|
||||
data_fabric_read32(0, DF_DRAM_BASE(dram_map_idx), IOMS0_FABRIC_ID);
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||||
data_fabric_read32(DF_DRAM_BASE(dram_map_idx), IOMS0_FABRIC_ID);
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||||
|
||||
if (dram_base_reg & DRAM_BASE_REG_VALID) {
|
||||
dram_limit_reg = data_fabric_read32(0, DF_DRAM_LIMIT(dram_map_idx),
|
||||
dram_limit_reg = data_fabric_read32(DF_DRAM_LIMIT(dram_map_idx),
|
||||
IOMS0_FABRIC_ID);
|
||||
memory_length =
|
||||
((dram_limit_reg & DRAM_LIMIT_ADDR) >> DRAM_LIMIT_ADDR_SHFT) + 1
|
||||
|
|
@ -85,7 +85,7 @@ static unsigned long gen_crat_memory_entries(struct acpi_crat_header *crat,
|
|||
}
|
||||
|
||||
if (dram_base_reg & DRAM_BASE_HOLE_EN) {
|
||||
dram_hole_ctl = data_fabric_read32(0, D18F0_DRAM_HOLE_CTL,
|
||||
dram_hole_ctl = data_fabric_read32(D18F0_DRAM_HOLE_CTL,
|
||||
IOMS0_FABRIC_ID);
|
||||
hole_base = (dram_hole_ctl & DRAM_HOLE_CTL_BASE);
|
||||
size_below_hole = hole_base - memory_base;
|
||||
|
|
|
|||
|
|
@ -3,20 +3,21 @@
|
|||
#ifndef AMD_PICASSO_DATA_FABRIC_H
|
||||
#define AMD_PICASSO_DATA_FABRIC_H
|
||||
|
||||
#include <amdblocks/data_fabric_defs.h>
|
||||
#include <types.h>
|
||||
|
||||
/* D18F0 - Fabric Configuration registers */
|
||||
#define D18F0_MMIO_BASE0 0x200
|
||||
#define D18F0_MMIO_LIMIT0 0x204
|
||||
#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0x200)
|
||||
#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0x204)
|
||||
#define D18F0_MMIO_SHIFT 16
|
||||
#define D18F0_MMIO_CTRL0 0x208
|
||||
#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0x208)
|
||||
|
||||
#define DF_MMIO_REG_SET_SIZE 4
|
||||
#define DF_MMIO_REG_SET_COUNT 8
|
||||
|
||||
#define DF_FICAA_BIOS 0x5C
|
||||
#define DF_FICAD_LO 0x98
|
||||
#define DF_FICAD_HI 0x9C
|
||||
#define DF_FICAA_BIOS DF_REG_ID(4, 0x5C)
|
||||
#define DF_FICAD_LO DF_REG_ID(4, 0x98)
|
||||
#define DF_FICAD_HI DF_REG_ID(4, 0x9C)
|
||||
|
||||
#define IOMS0_FABRIC_ID 9
|
||||
|
||||
|
|
@ -47,15 +48,15 @@ union df_ficaa {
|
|||
};
|
||||
|
||||
|
||||
#define D18F0_VGAEN 0x80
|
||||
#define D18F0_VGAEN DF_REG_ID(0, 0x80)
|
||||
#define VGA_ADDR_ENABLE BIT(0)
|
||||
|
||||
#define D18F0_DRAM_HOLE_CTL 0x104
|
||||
#define D18F0_DRAM_HOLE_CTL DF_REG_ID(0, 0x104)
|
||||
#define DRAM_HOLE_CTL_VALID BIT(0)
|
||||
#define DRAM_HOLE_CTL_BASE_SHFT 24
|
||||
#define DRAM_HOLE_CTL_BASE (0xff << DRAM_HOLE_CTL_BASE_SHFT)
|
||||
|
||||
#define D18F0_DRAM_BASE0 0x110
|
||||
#define D18F0_DRAM_BASE0 DF_REG_ID(0, 0x110)
|
||||
#define DRAM_BASE_REG_VALID BIT(0)
|
||||
#define DRAM_BASE_HOLE_EN BIT(1)
|
||||
#define DRAM_BASE_INTLV_CH_SHFT 4
|
||||
|
|
@ -65,7 +66,7 @@ union df_ficaa {
|
|||
#define DRAM_BASE_ADDR_SHFT 12
|
||||
#define DRAM_BASE_ADDR (0xfffff << DRAM_BASE_ADDR_SHFT)
|
||||
|
||||
#define D18F0_DRAM_LIMIT0 0x114
|
||||
#define D18F0_DRAM_LIMIT0 DF_REG_ID(0, 0x114)
|
||||
#define DRAM_LIMIT_DST_ID_SHFT 0
|
||||
#define DRAM_LIMIT_DST_ID (0xff << DRAM_LIMIT_DST_ID_SHFT)
|
||||
#define DRAM_LIMIT_INTLV_NUM_SOCK_SHFT 8
|
||||
|
|
|
|||
Loading…
Reference in New Issue