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mb/google/volteer: Configure Voxel USB2 ports for Type C 

Two USB2 ports 4 and 9 are assigned to type C connectors on Voxel board.
This update configures these USB2 ports for Type C which will allow USB2
port reset message upstream from PCH to CPU to recover a USB3 device
that downgraded to USB2 to upgrade back to USB3.

BUG=b:176575892
TEST=Booted to kernel on Voxel board and verified usb2 port reset
message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE
where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4.
Validated various USB3 devices enumeration.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia370a449a41701e690c1c507d70bedfce2076a65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
John Zhao 2021-01-01 14:51:04 -08:00 committed by Tim Wawrzynczak
parent 227055bdeb
commit 18a730d588
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/google/volteer/variants/voxel/overridetree.cb
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@ -13,6 +13,9 @@ chip soc/intel/tigerlake
.tdp_pl4 = 105, .tdp_pl4 = 105,
}" }"
register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Cl
register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C C0
# Disable SRCCLKREQ1# # Disable SRCCLKREQ1#
register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"