device/pciexp: Add support for PCIe CLK power management
Set PCIe "Enable Clock Power Management", if endpoint supports it. BUG=chrome-os-partner:31424 BRANCH=none TEST=build and boot on rambi, check Enable Clock Power Management in link control register is set properly Change-Id: Ie54110d1ef42184cfcf47c9fe4d735960aebe47f Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://chromium-review.googlesource.com/220742 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> [Edit commit message.] Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/8447 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -251,6 +251,14 @@ config PCIEXP_ASPM
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help
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help
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Detect and enable ASPM on PCIe links.
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Detect and enable ASPM on PCIe links.
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config PCIEXP_CLK_PM
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prompt "Enable PCIe Clock Power Management"
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bool
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depends on PCIEXP_PLUGIN_SUPPORT
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default n
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help
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Detect and enable Clock Power Management on PCIe.
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config PCI_BUS_SEGN_BITS
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config PCI_BUS_SEGN_BITS
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int
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int
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default 0
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default 0
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@ -90,6 +90,23 @@ static void pciexp_enable_common_clock(device_t root, unsigned root_cap,
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}
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}
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#endif /* CONFIG_PCIEXP_COMMON_CLOCK */
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#endif /* CONFIG_PCIEXP_COMMON_CLOCK */
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#if CONFIG_PCIEXP_CLK_PM
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static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap)
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{
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/* check if per port clk req is supported in device */
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u32 endp_ca;
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u16 lnkctl;
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endp_ca = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP);
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if ((endp_ca & PCI_EXP_CLK_PM) == 0) {
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printk(BIOS_INFO, "PCIE CLK PM is not supported by endpoint");
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return;
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}
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lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
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lnkctl = lnkctl | PCI_EXP_EN_CLK_PM;
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pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
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}
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#endif /* CONFIG_PCIEXP_CLK_PM */
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#if CONFIG_PCIEXP_ASPM
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#if CONFIG_PCIEXP_ASPM
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/*
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/*
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* Determine the ASPM L0s or L1 exit latency for a link
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* Determine the ASPM L0s or L1 exit latency for a link
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@ -200,6 +217,11 @@ static void pciexp_tune_dev(device_t dev)
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pciexp_enable_common_clock(root, root_cap, dev, cap);
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pciexp_enable_common_clock(root, root_cap, dev, cap);
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#endif
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#endif
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#if CONFIG_PCIEXP_CLK_PM
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/* Check if per port CLK req is supported by endpoint*/
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pciexp_enable_clock_power_pm(dev, cap);
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#endif
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#if CONFIG_PCIEXP_ASPM
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#if CONFIG_PCIEXP_ASPM
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/* Check for and enable ASPM */
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/* Check for and enable ASPM */
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enum aspm_type apmc = pciexp_enable_aspm(root, root_cap, dev, cap);
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enum aspm_type apmc = pciexp_enable_aspm(root, root_cap, dev, cap);
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@ -375,9 +375,11 @@
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#define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */
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#define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */
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#define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */
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#define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */
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#define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */
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#define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */
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#define PCI_EXP_CLK_PM 0x40000 /* Clock Power Management */
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#define PCI_EXP_LNKCTL 16 /* Link Control */
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#define PCI_EXP_LNKCTL 16 /* Link Control */
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#define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */
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#define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */
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#define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */
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#define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */
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#define PCI_EXP_EN_CLK_PM 0x100 /* Enable Clock Power Management */
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#define PCI_EXP_LNKSTA 18 /* Link Status */
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#define PCI_EXP_LNKSTA 18 /* Link Status */
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#define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */
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#define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */
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#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
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#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
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