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src/southbridge: Remove unnecessary semicolon 

Change-Id: I52c3ec75d44290b758b6e952344aa9a768bc2617
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16857
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2016-10-03 20:41:04 +02:00 committed by Kyösti Mälkki
parent 5c22825c19
commit 18cd8a64a4
7 changed files with 10 additions and 10 deletions
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2
src/southbridge/amd/cimx/sb700/smbus_spd.c
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@ -120,7 +120,7 @@ static void setupFch(UINT16 ioBase)
/* Enable SMBus MMIO. */ /* Enable SMBus MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2);
LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ; LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader);
PciData8 |= BIT0; PciData8 |= BIT0;
LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader); LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader);

2
src/southbridge/amd/rs690/pcie.c
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@ -310,7 +310,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
/* step 6d: ASPM L1 for the southbridge link */ /* step 6d: ASPM L1 for the southbridge link */
/* To enable L1s in the southbridge*/ /* To enable L1s in the southbridge*/
/* step 6e: ASPM L1 for GPP link(s) */; /* step 6e: ASPM L1 for GPP link(s) */
set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13); set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13);
set_pcie_enable_bits(dev, 0xa0, 3 << 12, 3 << 12); set_pcie_enable_bits(dev, 0xa0, 3 << 12, 3 << 12);
set_pcie_enable_bits(dev, 0xa0, 0xf << 4, 3 << 4); set_pcie_enable_bits(dev, 0xa0, 0xf << 4, 3 << 4);

4
src/southbridge/amd/sb600/early_setup.c
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@ -370,13 +370,13 @@ static void sb600_devices_por_init(void)
printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
/* I don't know why CIM tried to write into a read-only reg! */ /* I don't know why CIM tried to write into a read-only reg! */
/*pci_write_config8(dev, 0x0c, 0x20) */ ; /*pci_write_config8(dev, 0x0c, 0x20); */
/* Arbiter enable. */ /* Arbiter enable. */
pci_write_config8(dev, 0x43, 0xff); pci_write_config8(dev, 0x43, 0xff);
/* Set PCDMA request into height priority list. */ /* Set PCDMA request into height priority list. */
/* pci_write_config8(dev, 0x49, 0x1) */ ; /* pci_write_config8(dev, 0x49, 0x1); */
pci_write_config8(dev, 0x40, 0x26); pci_write_config8(dev, 0x40, 0x26);

2
src/southbridge/amd/sb700/early_setup.c
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@ -520,7 +520,7 @@ static void sb700_devices_por_init(void)
pci_write_config8(dev, 0x43, 0xff); pci_write_config8(dev, 0x43, 0xff);
/* Set PCDMA request into height priority list. */ /* Set PCDMA request into height priority list. */
/* pci_write_config8(dev, 0x49, 0x1) */ ; /* pci_write_config8(dev, 0x49, 0x1); */
pci_write_config8(dev, 0x40, 0x26); pci_write_config8(dev, 0x40, 0x26);

2
src/southbridge/amd/sb800/early_setup.c
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@ -468,7 +468,7 @@ static void sb800_devices_por_init(void)
pci_write_config8(dev, 0x43, 0xff); pci_write_config8(dev, 0x43, 0xff);
/* Set PCDMA request into height priority list. */ /* Set PCDMA request into height priority list. */
/* pci_write_config8(dev, 0x49, 0x1) */ ; /* pci_write_config8(dev, 0x49, 0x1); */
pci_write_config8(dev, 0x40, 0x26); pci_write_config8(dev, 0x40, 0x26);

4
src/southbridge/nvidia/mcp55/smbus.h
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@ -102,7 +102,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned
if (smbus_wait_until_done(smbus_io_base) < 0) { if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3; return -3;
} }
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
if (global_status_register != 0x80) { if (global_status_register != 0x80) {
return -1; return -1;
@ -163,7 +163,7 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned
if (smbus_wait_until_done(smbus_io_base) < 0) { if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3; return -3;
} }
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
if (global_status_register != 0x80) { if (global_status_register != 0x80) {
return -1; return -1;

4
src/southbridge/sis/sis966/early_smbus.c
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@ -109,7 +109,7 @@ int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char va
if (smbus_wait_until_done(smbus_io_base) < 0) { if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3; return -3;
} }
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
if (global_status_register != 0x80) { if (global_status_register != 0x80) {
return -1; return -1;
@ -176,7 +176,7 @@ static inline int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, u
if (smbus_wait_until_done(smbus_io_base) < 0) { if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3; return -3;
} }
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
if (global_status_register != 0x80) { if (global_status_register != 0x80) {
return -1; return -1;