mb/intel/kblrvp: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I8b30eb5d70c34ae3e2ed24ab52dd1357a54c5ae7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49439 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -12,7 +12,7 @@ static void early_config_gpio(void)
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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}
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void bootblock_mainboard_init(void)
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void bootblock_mainboard_early_init(void)
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{
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early_config_gpio();
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}
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@ -267,6 +267,8 @@ static const struct pad_config gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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};
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#endif
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@ -197,6 +197,8 @@ static const struct pad_config gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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};
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#endif
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@ -163,6 +163,8 @@ static const struct pad_config gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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};
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#endif
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