GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Update arima/hdama to detect how many nodes there are. Compare to tyan/s2892. 

Fixes booting for Hugh.

Various white space fixes as well.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2009-10-27 14:05:21 +00:00
parent a081a3b65f
commit 18d7c2e31e
1 changed files with 66 additions and 68 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

130
src/mainboard/arima/hdama/cache_as_ram_auto.c
View File

@ -95,7 +95,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
@ -103,40 +102,40 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
enumerate_ht_chain();
amd8111_enable_rom();
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
;
@ -149,71 +148,70 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const struct mem_controller cpu[] = {
{
.node_id = 0,
.f0 = PCI_DEV(0, 0x18, 0),
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
},
static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
{
.node_id = 1,
.f0 = PCI_DEV(0, 0x19, 0),
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
},
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
#endif
};
int needs_reset;
int needs_reset;
unsigned bsp_apicid = 0;
struct mem_controller ctrl[8];
unsigned nodes;
if (bist == 0) {
init_cpus(cpu_init_detectedx);
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx);
}
pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_default_resource_map();
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
// automatically set that for you, but you might meet tight space
needs_reset |= ht_setup_chains_x();
/* This is needed to be able to call udelay(). It could be moved to
* memreset_setup, since udelay is called in memreset. */
init_timer();
// automatically set that for you, but you might meet tight space
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
print_info("ht reset -\r\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
nodes = get_nodes();
fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
memreset_setup();
sdram_initialize(ARRAY_SIZE(cpu), cpu);
sdram_initialize(nodes, ctrl);
post_cache_as_ram();
}