baytrail: Change all SoC headers to <soc/headername.h> system

This patch aligns baytrail to the new SoC header include scheme.

BUG=None
TEST=Tested with whole series. Compiled Rambi.

Change-Id: I0f0a894f6f33449756582eefa0b50bae545220db
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1216a86538517c03a7e5bca547d08ff3dbcaa083
Original-Change-Id: If5d2a609354b3d773aa3d482e682ab97422fd9d5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/222026
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9363
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>

src/lib/reg_script.c

@@ -31,7 +31,7 @@
 #endif
 
 #if CONFIG_SOC_INTEL_BAYTRAIL
-#include <baytrail/iosf.h>
+#include <soc/iosf.h>	/* TODO: wrap in <soc/reg_script.h, remove #ifdef? */
 #endif
 
 #define POLL_DELAY 100 /* 100us */

src/mainboard/google/rambi/acpi_tables.c

@@ -30,9 +30,9 @@
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
-#include <baytrail/acpi.h>
-#include <baytrail/nvs.h>
-#include <baytrail/iomap.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include <soc/iomap.h>
 
 extern const unsigned char AmlCode[];
 

src/mainboard/google/rambi/chromeos.c

@@ -22,7 +22,7 @@
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <baytrail/gpio.h>
+#include <soc/gpio.h>
 
 #if CONFIG_EC_GOOGLE_CHROMEEC
 #include "ec.h"

src/mainboard/google/rambi/fadt.c

@@ -18,7 +18,7 @@
  */
 
 #include <string.h>
-#include <baytrail/acpi.h>
+#include <soc/acpi.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {

src/mainboard/google/rambi/gpio.c

@@ -18,7 +18,7 @@
  */
 
 #include <stdlib.h>
-#include <baytrail/gpio.h>
+#include <soc/gpio.h>
 #include "irqroute.h"
 
 /* TODO(SHAWNN): Modify gpios labeled 'INT' for interrupt handling */

src/mainboard/google/rambi/irqroute.h

@@ -17,9 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <soc/intel/baytrail/baytrail/irq.h>
-#include <soc/intel/baytrail/baytrail/pci_devs.h>
-#include <soc/intel/baytrail/baytrail/pmc.h>
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
 
 #define PCI_DEV_PIRQ_ROUTES \
 	PCI_DEV_PIRQ_ROUTE(GFX_DEV,  A, B, C, D), \

src/mainboard/google/rambi/mainboard.c

@@ -36,7 +36,7 @@
 #include <smbios.h>
 #include "ec.h"
 #include "onboard.h"
-#include <baytrail/gpio.h>
+#include <soc/gpio.h>
 #include <bootstate.h>
 
 void mainboard_suspend_resume(void)

src/mainboard/google/rambi/mainboard_smi.c

@@ -25,8 +25,8 @@
 #include <ec/google/chromeec/ec.h>
 #include "ec.h"
 
-#include <baytrail/nvs.h>
-#include <baytrail/pmc.h>
+#include <soc/nvs.h>
+#include <soc/pmc.h>
 
 /* The wake gpio is SUS_GPIO[0]. */
 #define WAKE_GPIO_EN SUS_GPIO_EN0

src/mainboard/google/rambi/romstage.c

@@ -21,9 +21,9 @@
 #include <string.h>
 #include <cbfs.h>
 #include <console/console.h>
-#include <baytrail/gpio.h>
-#include <baytrail/mrc_wrapper.h>
-#include <baytrail/romstage.h>
+#include <soc/gpio.h>
+#include <soc/mrc_wrapper.h>
+#include <soc/romstage.h>
 
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]

src/mainboard/google/rambi/w25q64.c

@@ -18,7 +18,7 @@
  */
 
 #include <string.h>
-#include <baytrail/spi.h>
+#include <soc/spi.h>
 
 /*
  * SPI lockdown configuration W25Q64FW.

src/soc/intel/baytrail/Makefile.inc

@@ -52,7 +52,7 @@ ramstage-y += hda.c
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
 
-CPPFLAGS_common += -Isrc/soc/intel/baytrail/
+CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
 
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware

src/soc/intel/baytrail/acpi.c

@@ -33,12 +33,12 @@
 #include <cpu/x86/tsc.h>
 #include <cpu/intel/turbo.h>
 
-#include <baytrail/acpi.h>
-#include <baytrail/iomap.h>
-#include <baytrail/irq.h>
-#include <baytrail/msr.h>
-#include <baytrail/pattrs.h>
-#include <baytrail/pmc.h>
+#include <soc/acpi.h>
+#include <soc/iomap.h>
+#include <soc/irq.h>
+#include <soc/msr.h>
+#include <soc/pattrs.h>
+#include <soc/pmc.h>
 
 #include <ec/google/chromeec/ec.h>
 #include <vendorcode/google/chromeos/gnvs.h>

src/soc/intel/baytrail/acpi/gpio.asl

@@ -19,8 +19,8 @@
  * MA 02110-1301 USA
  */
 
-#include <soc/intel/baytrail/baytrail/iomap.h>
-#include <soc/intel/baytrail/baytrail/irq.h>
+#include <soc/iomap.h>
+#include <soc/irq.h>
 
 /* SouthCluster GPIO */
 Device (GPSC)

src/soc/intel/baytrail/acpi/southcluster.asl

@@ -19,8 +19,8 @@
  * MA 02110-1301 USA
  */
 
-#include <soc/intel/baytrail/baytrail/iomap.h>
-#include <soc/intel/baytrail/baytrail/irq.h>
+#include <soc/iomap.h>
+#include <soc/irq.h>
 
 Scope(\)
 {

src/soc/intel/baytrail/bootblock/bootblock.c

@@ -21,7 +21,7 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
-#include <baytrail/iosf.h>
+#include <soc/iosf.h>
 #include <cpu/intel/microcode/microcode.c>
 
 static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type)

src/soc/intel/baytrail/chip.c

@@ -22,8 +22,8 @@
 #include <device/pci.h>
 #include <arch/pci_ops.h>
 
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 #include "chip.h"
 
 static void pci_domain_set_resources(device_t dev)

src/soc/intel/baytrail/cpu.c

@@ -30,11 +30,11 @@
 #include <cpu/x86/smm.h>
 #include <reg_script.h>
 
-#include <baytrail/iosf.h>
-#include <baytrail/msr.h>
-#include <baytrail/pattrs.h>
-#include <baytrail/ramstage.h>
-#include <baytrail/smm.h>
+#include <soc/iosf.h>
+#include <soc/msr.h>
+#include <soc/pattrs.h>
+#include <soc/ramstage.h>
+#include <soc/smm.h>
 
 static void smm_relocate(void *unused);
 static void enable_smis(void *unused);

src/soc/intel/baytrail/dptf.c

@@ -22,7 +22,7 @@
 #include <bootstate.h>
 #include <console/console.h>
 #include <reg_script.h>
-#include <baytrail/iosf.h>
+#include <soc/iosf.h>
 
 static const struct reg_script dptf_init_settings[] = {
 	/* SocThermInit */

src/soc/intel/baytrail/ehci.c

@@ -25,12 +25,12 @@
 #include <stdint.h>
 #include <reg_script.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/iosf.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/ramstage.h>
-#include <baytrail/ehci.h>
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/ramstage.h>
+#include <soc/ehci.h>
 
 #include "chip.h"
 

src/soc/intel/baytrail/elog.c

@@ -28,8 +28,8 @@
 #include <device/pci.h>
 #include <device/pci_ops.h>
 #include <elog.h>
-#include <baytrail/iomap.h>
-#include <baytrail/pmc.h>
+#include <soc/iomap.h>
+#include <soc/pmc.h>
 
 static void log_power_and_resets(const struct chipset_power_state *ps)
 {

src/soc/intel/baytrail/emmc.c

@@ -25,10 +25,10 @@
 #include <device/pci_ids.h>
 #include <reg_script.h>
 
-#include <baytrail/iosf.h>
-#include <baytrail/nvs.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/iosf.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 #include "chip.h"
 
 static const struct reg_script emmc_ops[] = {

src/soc/intel/baytrail/gfx.c

@@ -26,10 +26,10 @@
 #include <reg_script.h>
 #include <stdlib.h>
 
-#include <baytrail/gfx.h>
-#include <baytrail/iosf.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/gfx.h>
+#include <soc/iosf.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 
 #include "chip.h"
 

src/soc/intel/baytrail/gpio.c

@@ -19,9 +19,9 @@
 
 #include <device/pci.h>
 #include <console/console.h>
-#include <baytrail/gpio.h>
-#include <baytrail/pmc.h>
-#include <baytrail/smm.h>
+#include <soc/gpio.h>
+#include <soc/pmc.h>
+#include <soc/smm.h>
 
 /* GPIO-to-Pad LUTs */
 static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] =

src/soc/intel/baytrail/hda.c

@@ -25,10 +25,10 @@
 #include <reg_script.h>
 
 #include <soc/intel/common/hda_verb.h>
-#include <baytrail/iomap.h>
-#include <baytrail/iosf.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 
 static const struct reg_script init_ops[] = {
 	/* Enable no snoop traffic. */

src/soc/intel/baytrail/include/soc/acpi.h

@@ -21,7 +21,7 @@
 #define _BAYTRAIL_ACPI_H_
 
 #include <arch/acpi.h>
-#include <baytrail/nvs.h>
+#include <soc/nvs.h>
 
 void acpi_create_intel_hpet(acpi_hpet_t * hpet);
 void acpi_fill_in_fadt(acpi_fadt_t *fadt);

src/soc/intel/baytrail/include/soc/gpio.h

@@ -22,7 +22,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
-#include <baytrail/iomap.h>
+#include <soc/iomap.h>
 
 /* #define GPIO_DEBUG */
 

src/soc/intel/baytrail/include/soc/iosf.h

@@ -21,7 +21,7 @@
 #define _BAYTRAIL_IOSF_H_
 
 #include <stdint.h>
-#include <baytrail/pci_devs.h>
+#include <soc/pci_devs.h>
 
 /*
  * The Bay Trail SoC has a message network called IOSF Sideband. The access

src/soc/intel/baytrail/include/soc/nvs.h

@@ -22,7 +22,7 @@
 #define _BAYTRAIL_NVS_H_
 
 #include <vendorcode/google/chromeos/gnvs.h>
-#include <baytrail/device_nvs.h>
+#include <soc/device_nvs.h>
 
 typedef struct {
 	/* Miscellaneous */

src/soc/intel/baytrail/include/soc/ramstage.h

@@ -21,7 +21,7 @@
 #define _BAYTRAIL_RAMSTAGE_H_
 
 #include <device/device.h>
-#include <chip.h>
+#include <soc/intel/baytrail/chip.h>
 
 /* The baytrail_init_pre_device() function is called prior to device
  * initialization, but it's after console and cbmem has been reinitialized. */

src/soc/intel/baytrail/include/soc/romstage.h

@@ -26,7 +26,7 @@
 
 #include <stdint.h>
 #include <arch/cpu.h>
-#include <baytrail/mrc_wrapper.h>
+#include <soc/mrc_wrapper.h>
 
 struct romstage_params {
 	unsigned long bist;

src/soc/intel/baytrail/iosf.c

@@ -18,7 +18,7 @@
  */
 
 #include <arch/io.h>
-#include <baytrail/iosf.h>
+#include <soc/iosf.h>
 
 #if !defined(__PRE_RAM__)
 #define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12))

src/soc/intel/baytrail/lpe.c

@@ -25,14 +25,14 @@
 #include <device/pci_ids.h>
 #include <reg_script.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/iosf.h>
-#include <baytrail/lpc.h>
-#include <baytrail/nvs.h>
-#include <baytrail/pattrs.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/ramstage.h>
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/lpc.h>
+#include <soc/nvs.h>
+#include <soc/pattrs.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/ramstage.h>
 #include "chip.h"
 
 

src/soc/intel/baytrail/lpss.c

@@ -26,10 +26,10 @@
 #include <device/pci_ids.h>
 #include <reg_script.h>
 
-#include <baytrail/iosf.h>
-#include <baytrail/nvs.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/iosf.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 
 #include "chip.h"
 

src/soc/intel/baytrail/memmap.c

@@ -19,8 +19,8 @@
 
 #include <arch/io.h>
 #include <cbmem.h>
-#include <baytrail/iosf.h>
-#include <baytrail/smm.h>
+#include <soc/iosf.h>
+#include <soc/smm.h>
 
 uintptr_t smm_region_start(void)
 {

src/soc/intel/baytrail/northcluster.c

@@ -24,10 +24,10 @@
 #include <device/pci_ids.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/iosf.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 
 /* Host Memory Map:
  *

src/soc/intel/baytrail/pcie.c

@@ -24,10 +24,10 @@
 #include <device/pci_ids.h>
 #include <reg_script.h>
 
-#include <baytrail/pci_devs.h>
-#include <baytrail/pcie.h>
-#include <baytrail/ramstage.h>
-#include <baytrail/smm.h>
+#include <soc/pci_devs.h>
+#include <soc/pcie.h>
+#include <soc/ramstage.h>
+#include <soc/smm.h>
 
 #include "chip.h"
 

src/soc/intel/baytrail/perf_power.c

@@ -22,7 +22,7 @@
 #include <bootstate.h>
 #include <console/console.h>
 #include <reg_script.h>
-#include <baytrail/iosf.h>
+#include <soc/iosf.h>
 
 #define MAKE_MASK_INCLUSIVE(msb) \
 	((1ULL << (1 + (msb))) - 1)

src/soc/intel/baytrail/placeholders.c

@@ -2,7 +2,7 @@
 #include <arch/acpi.h>
 #include <cpu/cpu.h>
 #include <device/pci_rom.h>
-#include <baytrail/acpi.h>
+#include <soc/acpi.h>
 
 
 void smm_init(void) {}

src/soc/intel/baytrail/pmutil.c

@@ -21,10 +21,10 @@
 #include <arch/io.h>
 #include <console/console.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
 
 #if defined(__SMM__)
 

src/soc/intel/baytrail/ramstage.c

@@ -30,14 +30,14 @@
 #include <stdlib.h>
 #include <string.h>
 
-#include <baytrail/gpio.h>
-#include <baytrail/lpc.h>
-#include <baytrail/msr.h>
-#include <baytrail/nvs.h>
-#include <baytrail/pattrs.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/ramstage.h>
+#include <soc/gpio.h>
+#include <soc/lpc.h>
+#include <soc/msr.h>
+#include <soc/nvs.h>
+#include <soc/pattrs.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/ramstage.h>
 
 /* Global PATTRS */
 DEFINE_PATTRS;

src/soc/intel/baytrail/refcode.c

@@ -30,8 +30,8 @@
 #include <vendorcode/google/chromeos/vboot_handoff.h>
 #endif
 
-#include <baytrail/ramstage.h>
-#include <baytrail/efi_wrapper.h>
+#include <soc/ramstage.h>
+#include <soc/efi_wrapper.h>
 
 static inline struct ramstage_cache *next_cache(struct ramstage_cache *c)
 {

src/soc/intel/baytrail/reset.c

@@ -18,8 +18,8 @@
  */
 
 #include <arch/io.h>
-#include <baytrail/pmc.h>
-#include <baytrail/reset.h>
+#include <soc/pmc.h>
+#include <soc/reset.h>
 
 void cold_reset(void)
 {

src/soc/intel/baytrail/romstage/early_spi.c

@@ -22,9 +22,9 @@
 #include <delay.h>
 #include <console/console.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/romstage.h>
-#include <baytrail/spi.h>
+#include <soc/iomap.h>
+#include <soc/romstage.h>
+#include <soc/spi.h>
 
 #define SPI_CYCLE_DELAY 10 				/* 10us */
 #define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY	/* 400ms */

src/soc/intel/baytrail/romstage/gfx.c

@@ -18,9 +18,9 @@
  */
 
 #include <arch/io.h>
-#include <baytrail/gfx.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/romstage.h>
+#include <soc/gfx.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
 
 void gfx_init(void)
 {

src/soc/intel/baytrail/romstage/pmc.c

@@ -22,12 +22,12 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci_def.h>
-#include <baytrail/iomap.h>
-#include <baytrail/iosf.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/romstage.h>
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/romstage.h>
 #include "../chip.h"
 
 void tco_disable(void)

src/soc/intel/baytrail/romstage/raminit.c

@@ -25,13 +25,13 @@
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <halt.h>
-#include <baytrail/gpio.h>
+#include <soc/gpio.h>
 #include <soc/intel/common/mrc_cache.h>
-#include <baytrail/iomap.h>
-#include <baytrail/iosf.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/reset.h>
-#include <baytrail/romstage.h>
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/pci_devs.h>
+#include <soc/reset.h>
+#include <soc/romstage.h>
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 

src/soc/intel/baytrail/romstage/romstage.c

@@ -34,15 +34,15 @@
 #include <romstage_handoff.h>
 #include <timestamp.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#include <baytrail/gpio.h>
-#include <baytrail/iomap.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/reset.h>
-#include <baytrail/romstage.h>
-#include <baytrail/smm.h>
-#include <baytrail/spi.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/reset.h>
+#include <soc/romstage.h>
+#include <soc/smm.h>
+#include <soc/spi.h>
 
 /* The cache-as-ram assembly file calls romstage_main() after setting up
  * cache-as-ram.  romstage_main() will then call the mainboards's

src/soc/intel/baytrail/romstage/uart.c

@@ -18,11 +18,11 @@
  */
 
 #include <arch/io.h>
-#include <baytrail/gpio.h>
-#include <baytrail/iomap.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/romstage.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
 
 void byt_config_com1_and_enable(void)
 {

src/soc/intel/baytrail/sata.c

@@ -18,9 +18,9 @@
  */
 
 #include <arch/io.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
-#include <baytrail/sata.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/sata.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/device.h>

src/soc/intel/baytrail/scc.c

@@ -25,9 +25,9 @@
 #include <device/pci_ids.h>
 #include <reg_script.h>
 
-#include <baytrail/iosf.h>
-#include <baytrail/nvs.h>
-#include <baytrail/ramstage.h>
+#include <soc/iosf.h>
+#include <soc/nvs.h>
+#include <soc/ramstage.h>
 
 static const struct reg_script scc_start_dll[] = {
 	/* Configure master DLL. */

src/soc/intel/baytrail/sd.c

@@ -24,10 +24,10 @@
 #include <device/pci_ids.h>
 #include <reg_script.h>
 
-#include <baytrail/iosf.h>
-#include <baytrail/nvs.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/iosf.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 #include "chip.h"
 
 #define CAP_OVERRIDE_LOW 0xa0

src/soc/intel/baytrail/smihandler.c

@@ -28,9 +28,9 @@
 #include <halt.h>
 #include <spi-generic.h>
 
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/nvs.h>
 
 /* GNVS needs to be set by coreboot initiating a software SMI. */
 static global_nvs_t *gnvs;

src/soc/intel/baytrail/smm.c

@@ -27,9 +27,9 @@
 #include <cpu/x86/smm.h>
 #include <string.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/pmc.h>
-#include <baytrail/smm.h>
+#include <soc/iomap.h>
+#include <soc/pmc.h>
+#include <soc/smm.h>
 
 /* Save settings which will be committed in SMI functions. */
 static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT];

src/soc/intel/baytrail/southcluster.c

@@ -31,14 +31,14 @@
 #include <pc80/mc146818rtc.h>
 #include <drivers/uart/uart8250reg.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/irq.h>
-#include <baytrail/lpc.h>
-#include <baytrail/nvs.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/ramstage.h>
-#include <baytrail/spi.h>
+#include <soc/iomap.h>
+#include <soc/irq.h>
+#include <soc/lpc.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/ramstage.h>
+#include <soc/spi.h>
 #include "chip.h"
 
 static inline void

src/soc/intel/baytrail/spi.c

@@ -31,8 +31,8 @@
 #include <device/pci_ids.h>
 #include <spi_flash.h>
 
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
 
 #ifdef __SMM__
 #define pci_read_config_byte(dev, reg, targ)\

src/soc/intel/baytrail/stage_cache.c

@@ -19,7 +19,7 @@
 
 #include <cbmem.h>
 #include <ramstage_cache.h>
-#include <baytrail/smm.h>
+#include <soc/smm.h>
 
 struct ramstage_cache *ramstage_cache_location(long *size)
 {

src/soc/intel/baytrail/tsc_freq.c

@@ -20,7 +20,7 @@
 #include <stdint.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/tsc.h>
-#include <baytrail/msr.h>
+#include <soc/msr.h>
 
 unsigned bus_freq_khz(void)
 {
@@ -53,9 +53,9 @@ unsigned long tsc_freq_mhz(void)
 
 #if !defined(__SMM__)
 #if !defined(__PRE_RAM__)
-#include <baytrail/ramstage.h>
+#include <soc/ramstage.h>
 #else
-#include <baytrail/romstage.h>
+#include <soc/romstage.h>
 #endif
 
 void set_max_freq(void)

src/soc/intel/baytrail/xhci.c

@@ -25,14 +25,14 @@
 #include <stdint.h>
 #include <reg_script.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/iosf.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pattrs.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/ramstage.h>
-#include <baytrail/xhci.h>
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/lpc.h>
+#include <soc/pattrs.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/ramstage.h>
+#include <soc/xhci.h>
 
 #include "chip.h"