mb/lenovo/t420(s): Do minor cosmetic changes
Align the whitespace and do some cosmetic changes. This makes it easier to fold these two boards into a variant setup. Change-Id: I53bdd90ae47b52dfdfec27229c6b904487fa2081 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -74,8 +74,8 @@ entries
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# coreboot config options: northbridge
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432 3 e 11 gfx_uma_size
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435 2 e 12 hybrid_graphics_mode
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#437 3 r 0 unused
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435 2 e 12 hybrid_graphics_mode
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#437 3 r 0 unused
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440 8 h 0 volume
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@ -16,10 +16,10 @@ config BOARD_SPECIFIC_OPTIONS
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select HAVE_CMOS_DEFAULT
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select HAVE_ACPI_RESUME
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select INTEL_INT15
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select MAINBOARD_HAS_LIBGFXINIT
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select GFX_GMA_PANEL_1_ON_LVDS
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM1
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select MAINBOARD_HAS_LIBGFXINIT
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select GFX_GMA_PANEL_1_ON_LVDS
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select DRIVERS_LENOVO_HYBRID_GRAPHICS
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select INTEL_GMA_HAVE_VBT
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select MAINBOARD_USES_IFD_GBE_REGION
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@ -1,4 +1,5 @@
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chip northbridge/intel/sandybridge
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# IGD Displays
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register "gfx" = "GMA_STATIC_DISPLAYS(1)"
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# Enable DisplayPort Hotplug with 6ms pulse
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@ -66,6 +67,7 @@ chip northbridge/intel/sandybridge
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register "c2_latency" = "101" # c2 not supported
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# device specific SPI configuration
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register "spi_uvscc" = "0x2005"
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register "spi_lvscc" = "0x2005"
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@ -35,8 +35,8 @@ static void hybrid_graphics_init(void)
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}
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 0, 1, -1 }, /* P0 empty */
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{ 1, 1, 1 }, /* P1 system port 2 (To system port) (EHCI debug), OC 1 */
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{ 0, 1, -1 }, /* P0: empty */
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{ 1, 1, 1 }, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */
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{ 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */
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{ 1, 0, -1 }, /* P3: WWAN, no OC */
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{ 1, 1, -1 }, /* P4: smartcard, no OC */
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@ -2,6 +2,7 @@
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/* This file is part of the coreboot project. */
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#include <southbridge/intel/common/gpio.h>
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static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_GPIO, // -USB30_SMIB - input
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.gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input
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@ -69,7 +70,7 @@ static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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.gpio28 = GPIO_DIR_OUTPUT,
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.gpio29 = GPIO_DIR_OUTPUT,
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.gpio30 = GPIO_DIR_OUTPUT,
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.gpio31 = GPIO_DIR_INPUT
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.gpio31 = GPIO_DIR_INPUT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_level = {
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@ -108,8 +109,8 @@ static const struct pch_gpio_set1 pch_gpio_set1_level = {
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};
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static const struct pch_gpio_set1 pch_gpio_set1_invert = {
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.gpio0 = GPIO_INVERT,
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.gpio1 = GPIO_INVERT,
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.gpio0 = GPIO_INVERT,
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.gpio1 = GPIO_INVERT,
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.gpio13 = GPIO_INVERT,
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};
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@ -6,8 +6,8 @@
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#include <cpu/x86/smm.h>
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#include <ec/acpi/ec.h>
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#include <ec/lenovo/h8/h8.h>
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#include <southbridge/intel/common/pmutil.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/pmutil.h>
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#define GPE_EC_SCI 1
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#define GPE_EC_WAKE 13
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