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AMD: Drop six copies of wrmsr_amd and rdmsr_amd 

Based on comments in cpu/x86/msr.h for wrmsr/rdmsr, and for symmetry,
I have added __attribute__((always_inline)) for these.

Change-Id: Ia0a34c15241f9fbc8c78763386028ddcbe6690b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/2898
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Kyösti Mälkki 2013-03-25 12:48:49 +02:00 committed by Marc Jones
parent 4d6ab4e2ae
commit 190011e47c
16 changed files with 24 additions and 167 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
src/cpu/amd/agesa/family10/model_10_init.c
View File

@ -35,26 +35,6 @@
#define MCI_STATUS 0x401
static msr_t rdmsr_amd(u32 index)
{
msr_t result;
__asm__ __volatile__(
"rdmsr"
:"=a"(result.lo), "=d"(result.hi)
:"c"(index), "D"(0x9c5a203a)
);
return result;
}
static void wrmsr_amd(u32 index, msr_t msr)
{
__asm__ __volatile__(
"wrmsr"
: /* No outputs */
:"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
);
}
static void model_10_init(device_t dev)
{
printk(BIOS_DEBUG, "Model 10 Init - a no-op.\n");

20
src/cpu/amd/agesa/family12/model_12_init.c
View File

@ -36,26 +36,6 @@
#define MCI_STATUS 0x401
msr_t rdmsr_amd(u32 index)
{
msr_t result;
__asm__ __volatile__(
"rdmsr"
:"=a"(result.lo), "=d"(result.hi)
:"c"(index), "D"(0x9c5a203a)
);
return result;
}
void wrmsr_amd(u32 index, msr_t msr)
{
__asm__ __volatile__(
"wrmsr"
: /* No outputs */
:"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
);
}
static void model_12_init(device_t dev)
{
printk(BIOS_DEBUG, "Model 12 Init - a no-op.\n");

20
src/cpu/amd/agesa/family14/model_14_init.c
View File

@ -39,26 +39,6 @@
#define MCI_STATUS 0x401
msr_t rdmsr_amd(u32 index)
{
msr_t result;
__asm__ __volatile__(
"rdmsr"
:"=a"(result.lo), "=d"(result.hi)
:"c"(index), "D"(0x9c5a203a)
);
return result;
}
void wrmsr_amd(u32 index, msr_t msr)
{
__asm__ __volatile__(
"wrmsr"
: /* No outputs */
:"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
);
}
static void model_14_init(device_t dev)
{
u32 i;

20
src/cpu/amd/agesa/family15/model_15_init.c
View File

@ -32,26 +32,6 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/amdfam15.h>
msr_t rdmsr_amd(u32 index)
{
msr_t result;
__asm__ __volatile__(
"rdmsr"
:"=a"(result.lo), "=d"(result.hi)
:"c"(index), "D"(0x9c5a203a)
);
return result;
}
void wrmsr_amd(u32 index, msr_t msr)
{
__asm__ __volatile__(
"wrmsr"
: /* No outputs */
:"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
);
}
static void model_15_init(device_t dev)
{
printk(BIOS_DEBUG, "Model 15 Init.\n");

20
src/cpu/amd/agesa/family15tn/model_15_init.c
View File

@ -37,26 +37,6 @@
#include <cpu/amd/agesa/s3_resume.h>
#endif
msr_t rdmsr_amd(u32 index)
{
msr_t result;
__asm__ __volatile__(
"rdmsr"
:"=a"(result.lo), "=d"(result.hi)
:"c"(index), "D"(0x9c5a203a)
);
return result;
}
void wrmsr_amd(u32 index, msr_t msr)
{
__asm__ __volatile__(
"wrmsr"
: /* No outputs */
:"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
);
}
static void model_15_init(device_t dev)
{
printk(BIOS_DEBUG, "Model 15 Init.\n");

20
src/cpu/amd/model_10xxx/model_10xxx_init.c
View File

@ -38,26 +38,6 @@
#define MCI_STATUS 0x401
msr_t rdmsr_amd(u32 index)
{
msr_t result;
__asm__ __volatile__(
"rdmsr"
:"=a"(result.lo), "=d"(result.hi)
:"c"(index), "D"(0x9c5a203a)
);
return result;
}
void wrmsr_amd(u32 index, msr_t msr)
{
__asm__ __volatile__(
"wrmsr"
: /* No outputs */
:"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
);
}
static void model_10xxx_init(device_t dev)
{
u8 i;

3
src/cpu/amd/model_10xxx/processor_name.c
View File

@ -29,11 +29,10 @@
#include <console/console.h>
#include <string.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/cpu.h>
#include <cpu/amd/model_10xxx_rev.h>
extern void wrmsr_amd(u32 index, msr_t msr);
/* The maximum length of CPU names is 48 bytes, including the final NULL byte.
* If you change these names your BIOS will _NOT_ pass the AMD validation and
* your mainboard will not be posted on the AMD Recommended Motherboard Website

20
src/cpu/amd/model_fxx/model_fxx_init.c
View File

@ -80,26 +80,6 @@ int is_cpu_f0_in_bsp(int nodeid)
#define MCI_STATUS 0x401
static inline msr_t rdmsr_amd(u32 index)
{
msr_t result;
__asm__ __volatile__(
"rdmsr"
:"=a"(result.lo), "=d"(result.hi)
:"c"(index), "D"(0x9c5a203a)
);
return result;
}
static inline void wrmsr_amd(u32 index, msr_t msr)
{
__asm__ __volatile__(
"wrmsr"
: /* No outputs */
:"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
);
}
#define MTRR_COUNT 8
#define ZERO_CHUNK_KB 0x800UL /* 2M */
#define TOLM_KB 0x400000UL

12
src/cpu/amd/model_fxx/processor_name.c
View File

@ -35,6 +35,7 @@
#include <console/console.h>
#include <string.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/model_fxx_rev.h>
/* The maximum length of CPU names is 48 bytes, including the final NULL byte.
@ -100,17 +101,6 @@ static const char *processor_names[]={
};
#endif
/* wrmsr_amd() is from yhlu's changes to model_fxx_init.c */
static inline void wrmsr_amd(unsigned index, msr_t msr)
{
__asm__ __volatile__ (
"wrmsr"
: /* No outputs */
: "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a)
);
}
int init_processor_name(void)
{
#if !CONFIG_K8_REV_F_SUPPORT

2
src/cpu/amd/mtrr/amd_mtrr.c
View File

@ -2,9 +2,9 @@
#include <device/device.h>
#include <arch/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
/* These will likely move to some device node or cbmem. */
static uint64_t amd_topmem = 0;

2
src/cpu/x86/mtrr/earlymtrr.c
View File

@ -2,8 +2,8 @@
#define EARLYMTRR_C
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
static void set_var_mtrr(
unsigned reg, unsigned base, unsigned size, unsigned type)

3
src/include/cpu/amd/amdfam12.h
View File

@ -33,9 +33,6 @@
#define CPU_ID_FEATURES_MSR 0xC0011004
#define CPU_ID_EXT_FEATURES_MSR 0xC0011005
msr_t rdmsr_amd(u32 index);
void wrmsr_amd(u32 index, msr_t msr);
//#if defined(__GNUC__)
//// it can be used to get unitid and coreid it running only
//struct node_core_id get_node_core_id(u32 nb_cfg_54);

3
src/include/cpu/amd/amdfam14.h
View File

@ -33,9 +33,6 @@
#define CPU_ID_FEATURES_MSR 0xC0011004
#define CPU_ID_EXT_FEATURES_MSR 0xC0011005
msr_t rdmsr_amd(u32 index);
void wrmsr_amd(u32 index, msr_t msr);
#if defined(__PRE_RAM__)
void wait_all_core0_started(void);
void wait_all_other_cores_started(u32 bsp_apicid);

3
src/include/cpu/amd/amdfam15.h
View File

@ -35,9 +35,6 @@
#define CPU_ID_FEATURES_MSR 0xC0011004
#define CPU_ID_EXT_FEATURES_MSR 0xC0011005
msr_t rdmsr_amd(u32 index);
void wrmsr_amd(u32 index, msr_t msr);
#if defined(__PRE_RAM__)
void wait_all_core0_started(void);
void wait_all_other_cores_started(u32 bsp_apicid);

3
src/include/cpu/amd/model_10xxx_msr.h
View File

@ -39,7 +39,4 @@
#define LOGICAL_CPUS_NUM_MSR 0xC001100d
#define CPU_ID_EXT_FEATURES_MSR 0xC0011005
msr_t rdmsr_amd(u32 index);
void wrmsr_amd(u32 index, msr_t msr);
#endif /* CPU_AMD_MODEL_10XXX_MSR_H */

20
src/include/cpu/amd/mtrr.h
View File

@ -40,6 +40,26 @@
#if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__)
void amd_setup_mtrrs(void);
static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned index)
{
msr_t result;
__asm__ __volatile__ (
"rdmsr"
: "=a" (result.lo), "=d" (result.hi)
: "c"(index), "D"(0x9c5a203a)
);
return result;
}
static inline __attribute__((always_inline)) void wrmsr_amd(unsigned index, msr_t msr)
{
__asm__ __volatile__ (
"wrmsr"
: /* No outputs */
: "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a)
);
}
/* To distribute topmem MSRs to APs. */
void setup_bsp_ramtop(void);
uint64_t bsp_topmem(void);