GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

src/soc/intel/braswell/include/soc/irq.h: Change PIRQ_PIC_IRQDISABLE value 

Using 0 for PIRQ_PIC_IRQDISABLE might conflict with using IRQ0 as PIRQ.
Change PIRQ_PIC_IRQDISABLE value to 0x80, so value 0 is reserved for IRQ0.

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: I18706f12e7c2293e948eb10818393f0d1870f514
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29393
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Frans Hendriks 2018-10-31 13:58:26 +01:00 committed by Patrick Georgi
parent 624195e454
commit 190e5bee4a
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/intel/braswell/include/soc/irq.h
View File

@ -3,6 +3,7 @@
* *
* Copyright (C) 2013 Google Inc. * Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp. * Copyright (C) 2015 Intel Corp.
* Copyright (C) 2018 Eltan B.V.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -142,7 +143,7 @@
/* PIC IRQ settings. */ /* PIC IRQ settings. */
#define PIRQ_PIC_IRQDISABLE 0x0 #define PIRQ_PIC_IRQDISABLE 0x80
#define PIRQ_PIC_IRQ3 0x3 #define PIRQ_PIC_IRQ3 0x3
#define PIRQ_PIC_IRQ4 0x4 #define PIRQ_PIC_IRQ4 0x4
#define PIRQ_PIC_IRQ5 0x5 #define PIRQ_PIC_IRQ5 0x5