diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 592a316e06..a3076a8035 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -68,6 +68,18 @@ static void chip_final(void *data)
 {
 	/* Lock SBI */
 	pci_or_config32(PCH_DEV_P2SB, P2SBC, SBILOCK);
+
+	/* LOCK PAM */
+	pci_or_config32(pcidev_path_on_root(PCI_DEVFN(0, 0)), 0x80, 1 << 0);
+
+	/*
+	 * LOCK SMRAM
+	 * According to the CedarIsland FSP Integration Guide this needs to
+	 * be done with legacy 0xCF8/0xCFC IO ops.
+	 */
+	uint8_t reg8 = pci_io_read_config8(PCI_DEV(0, 0, 0), 0x88);
+	pci_io_write_config8(PCI_DEV(0, 0, 0), 0x88, reg8 | (1 << 4));
+
 	p2sb_hide();
 
 	set_bios_init_completion();