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soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE

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According to the latest Alderlake Platform FSP Integration Guide, the
minimum amount of stack needed for FSP-M is 512KiB. Change
DCACHE_RAM_SIZE and DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB
previously determined empirically).

TEST=Able to pass FSP-M MRC training on LPDDR5 SKU without any hang.

Change-Id: Ic831ca9110a15fdb48ad31a7db396740811bf0f2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2020-11-21 19:30:57 +05:30
parent 6de5bf6698
commit 191bd82734
1 changed files with 3 additions and 3 deletions
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6
src/soc/intel/alderlake/Kconfig
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@ -70,18 +70,18 @@ config DCACHE_RAM_BASE
default 0xfef00000 default 0xfef00000
config DCACHE_RAM_SIZE config DCACHE_RAM_SIZE
default 0x80000 default 0xc0000
help help
The size of the cache-as-ram region required during bootblock The size of the cache-as-ram region required during bootblock
and/or romstage. and/or romstage.
config DCACHE_BSP_STACK_SIZE config DCACHE_BSP_STACK_SIZE
hex hex
default 0x40400 default 0x80400
help help
The amount of anticipated stack usage in CAR by bootblock and The amount of anticipated stack usage in CAR by bootblock and
other stages. In the case of FSP_USES_CB_STACK default value will be other stages. In the case of FSP_USES_CB_STACK default value will be
sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement
(~1KiB). (~1KiB).
config FSP_TEMP_RAM_SIZE config FSP_TEMP_RAM_SIZE