From 192b57cc8bf6d8a04bf20fa0270af4acceba42e9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 12 Jul 2020 20:48:45 +0200 Subject: [PATCH] amd/{hudson,stoney,picasso}: Drop PM2 settings from FADT The PM2_CNT register block is no longer needed, as explained in some comments. While they may have been copy-pasted around a lot, they are at least true for Hudson, and it makes sense to assume that they are true for newer chipsets as well. As per the ACPI specification, version 6.3, section 4.8.1.3 (PM2 Control Register): This register block is optional, if not supported its block pointer and length contain a value of zero. Since the FADT struct defaults to zero in coreboot, we don't need to do anything to indicate PM2_CNT is not supported. So, drop unneeded values. Change-Id: Iabc7985c84aabe40ad98fdc9fc6ccbbab0a516c1 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43381 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/acpi.c | 13 ------------- src/soc/amd/stoneyridge/acpi.c | 13 ------------- src/southbridge/amd/agesa/hudson/fadt.c | 13 ------------- src/southbridge/amd/pi/hudson/fadt.c | 13 ------------- 4 files changed, 52 deletions(-) diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index afd9f48774..90ea8250e4 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -100,13 +100,11 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; - fadt->pm2_cnt_blk = 0x0000; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; fadt->gpe0_blk = ACPI_GPE0_BLK; fadt->pm1_evt_len = 4; /* 32 bits */ fadt->pm1_cnt_len = 2; /* 16 bits */ - fadt->pm2_cnt_len = 0; fadt->pm_tmr_len = 4; /* 32 bits */ fadt->gpe0_blk_len = 8; /* 64 bits */ @@ -164,17 +162,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; - /* - * Note: Under this current AMD C state implementation, this is no - * longer used and should not be reported to OS. - */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = 0; - fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 0ffeb04ed7..797dece0ef 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -72,13 +72,11 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; - fadt->pm2_cnt_blk = 0x0000; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; fadt->gpe0_blk = ACPI_GPE0_BLK; fadt->pm1_evt_len = 4; /* 32 bits */ fadt->pm1_cnt_len = 2; /* 16 bits */ - fadt->pm2_cnt_len = 0; fadt->pm_tmr_len = 4; /* 32 bits */ fadt->gpe0_blk_len = 8; /* 64 bits */ @@ -136,17 +134,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; - /* - * Note: Under this current AMD C state implementation, this is no - * longer used and should not be reported to OS. - */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = 0; - fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index e5791fe374..47835c4685 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -36,13 +36,11 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; - fadt->pm2_cnt_blk = 0x0000; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; fadt->gpe0_blk = ACPI_GPE0_BLK; fadt->pm1_evt_len = 4; /* 32 bits */ fadt->pm1_cnt_len = 2; /* 16 bits */ - fadt->pm2_cnt_len = 0; fadt->pm_tmr_len = 4; /* 32 bits */ fadt->gpe0_blk_len = 8; /* 64 bits */ @@ -97,17 +95,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; - /* - * Note: Under this current AMD C state implementation, this is no longer - * used and should not be reported to OS. - */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = 0; - fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 16052dc81f..544677983f 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -36,13 +36,11 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; - fadt->pm2_cnt_blk = 0x0000; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; fadt->gpe0_blk = ACPI_GPE0_BLK; fadt->pm1_evt_len = 4; /* 32 bits */ fadt->pm1_cnt_len = 2; /* 16 bits */ - fadt->pm2_cnt_len = 0; fadt->pm_tmr_len = 4; /* 32 bits */ fadt->gpe0_blk_len = 8; /* 64 bits */ @@ -100,17 +98,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; - /* - * Note: Under this current AMD C state implementation, this is no longer - * used and should not be reported to OS. - */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = 0; - fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32;