google/oak: elm: Update the differences between oak-rev6 and elm-rev0
- Remove the deprecated revison settings. - Change LID pin to SPI_CK. - Add i2c bus number and i2c slave address for elm. - Skip the pin configurations(ALC5514 and USB OC pins) belonging to Oak. - Add Hynix 4GB DRAM config BRANCH=none BUG=chrome-os-partner:51725 TEST=boot to kernel on elm-rev0 Change-Id: Ifaedd115c84d095ee289b576ff76af6b0aa3e545 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2ed4543cdc7e84a0463b73dda96027270ec30272 Original-Change-Id: Id957374d7a67b8c72df1d07a6cecc1064d4e0356 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332733 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14692 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Yidi Lin
Patrick Georgi
parent
9a57095bd2
commit
19318ddab5
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@ -83,6 +83,6 @@ config GBB_HWID
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config BOARD_ID_ADJUSTMENT
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int
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default 0 if BOARD_GOOGLE_OAK
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default 6
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default 7
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endif # BOARD_GOOGLE_OAK
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@ -17,8 +17,11 @@
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#define __MAINBOARD_GOOGLE_OAK_GPIO_H__
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#include <soc/pinmux.h>
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#define LID ((board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7) ? \
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PAD_EINT12 : PAD_SPI_CK)
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enum {
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LID = PAD_EINT12,
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/* Board ID related GPIOS. */
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BOARD_ID_0 = PAD_RDN3_A,
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BOARD_ID_1 = PAD_RDP3_A,
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@ -87,12 +87,23 @@ static void configure_audio(void)
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gpio_set_mode(PAD_I2S0_MCK, PAD_I2S0_MCK_FUNC_I2S1_MCK);
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gpio_set_mode(PAD_I2S0_DATA0, PAD_I2S0_DATA0_FUNC_I2S1_DO_1);
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gpio_set_mode(PAD_I2S0_DATA1, PAD_I2S0_DATA1_FUNC_I2S2_DI_2);
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if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT >= 5)
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gpio_set_mode(PAD_UCTS0, PAD_UCTS0_FUNC_I2S2_DI_1);
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/* codec ext MCLK ON */
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mt6391_gpio_output(MT6391_KP_COL4, 1);
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mt6391_gpio_output(MT6391_KP_COL5, 1);
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switch (board_id() + CONFIG_BOARD_ID_ADJUSTMENT) {
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case 2:
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case 3:
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case 4:
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mt6391_gpio_output(MT6391_KP_COL5, 1);
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break;
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case 5:
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case 6:
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gpio_set_mode(PAD_UCTS0, PAD_UCTS0_FUNC_I2S2_DI_1);
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mt6391_gpio_output(MT6391_KP_COL5, 1);
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break;
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default:
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break;
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}
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/* Init i2c bus Timing register for audio codecs */
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mtk_i2c_bus_init(CODEC_I2C_BUS);
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@ -111,10 +122,13 @@ static void configure_usb(void)
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/* Configure USB OC pins*/
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gpio_input_pullup(PAD_MSDC3_DSL);
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gpio_input_pullup(PAD_CMPCLK);
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gpio_input_pullup(PAD_PCM_SYNC);
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if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7)
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gpio_input_pullup(PAD_PCM_SYNC);
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}
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if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4) {
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if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4 &&
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board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7)
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{
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/* USB 2.0 type A port over current interrupt pin(low active) */
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gpio_input_pullup(PAD_UCTS2);
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/* USB 2.0 type A port BC1.2 STATUS(low active) */
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@ -134,9 +148,6 @@ static void configure_backlight(void)
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{
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/* Configure PANEL_LCD_POWER_EN */
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switch (board_id() + CONFIG_BOARD_ID_ADJUSTMENT) {
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case 1:
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case 2:
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break;
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case 3:
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gpio_output(PAD_UCTS2, 0);
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break;
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@ -156,69 +167,47 @@ static void configure_display(void)
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{
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mtcmos_display_power_on();
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switch (board_id() + CONFIG_BOARD_ID_ADJUSTMENT) {
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case 0:
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/* board from Rev0, Rev1 */
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/* vgp2 set to 1.8V for it6151 */
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mt6391_configure_ldo(LDO_VGP2, LDO_1P8);
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gpio_output(PAD_PCM_RX, 0); /* IT6151_SYSRSTN */
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gpio_output(PAD_CMMCLK, 1); /* PANEL_3V3_ENABLE */
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gpio_output(PAD_PCM_SYNC, 1); /* IT6151_1V2_ENABLE */
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gpio_output(PAD_PCM_RX, 1); /* IT6151_SYSRSTN */
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break;
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case 1:
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/* board from Rev0, Rev1 */
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/* vgp2 set to 1.8V for it6151 */
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mt6391_configure_ldo(LDO_VGP2, LDO_1P8);
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gpio_output(PAD_URTS0, 0); /* IT6151_SYSRSTN */
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gpio_output(PAD_URTS2, 1); /* IT6151_1V2_ENABLE */
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gpio_output(PAD_CMMCLK, 1); /* PANEL_3V3_ENABLE */
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gpio_output(PAD_URTS0, 1); /* IT6151_SYSRSTN */
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break;
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default:
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/* board from Rev2 */
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gpio_output(PAD_CMMCLK, 1); /* PANEL_3V3_ENABLE */
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/* vgp2 set to 3.3V for ps8640 */
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mt6391_configure_ldo(LDO_VGP2, LDO_3P3);
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gpio_output(PAD_URTS0, 0); /* PS8640_SYSRSTN */
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/* PS8640_1V2_ENABLE */
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if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT == 4)
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gpio_output(PAD_SRCLKENAI2, 1);
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else
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gpio_output(PAD_URTS2, 1);
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/* delay 2ms for vgp2 and PS8640_1V2_ENABLE stable */
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mdelay(2);
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/* PS8640_PDN */
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if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4)
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gpio_output(PAD_LCM_RST, 1);
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else
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gpio_output(PAD_UCTS0, 1);
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gpio_output(PAD_PCM_CLK, 1); /* PS8640_MODE_CONF */
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gpio_output(PAD_URTS0, 1); /* PS8640_SYSRSTN */
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/* for level shift(1.8V to 3.3V) on */
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udelay(100);
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}
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/* board from Rev2 */
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gpio_output(PAD_CMMCLK, 1); /* PANEL_3V3_ENABLE */
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/* vgp2 set to 3.3V for ps8640 */
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mt6391_configure_ldo(LDO_VGP2, LDO_3P3);
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gpio_output(PAD_URTS0, 0); /* PS8640_SYSRSTN */
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/* PS8640_1V2_ENABLE */
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if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT == 4)
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gpio_output(PAD_SRCLKENAI2, 1);
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else
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gpio_output(PAD_URTS2, 1);
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/* delay 2ms for vgp2 and PS8640_1V2_ENABLE stable */
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mdelay(2);
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/* PS8640_PDN */
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if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4)
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gpio_output(PAD_LCM_RST, 1);
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else
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gpio_output(PAD_UCTS0, 1);
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gpio_output(PAD_PCM_CLK, 1); /* PS8640_MODE_CONF */
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gpio_output(PAD_URTS0, 1); /* PS8640_SYSRSTN */
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/* for level shift(1.8V to 3.3V) on */
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udelay(100);
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}
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static void display_startup(void)
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{
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struct edid edid;
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u8 i2c_bus;
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u8 i2c_bus, i2c_addr;
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int ret;
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switch (board_id() + CONFIG_BOARD_ID_ADJUSTMENT) {
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case 0:
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case 1:
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i2c_bus = 3;
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break;
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default:
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if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 6) {
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i2c_bus = 0;
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i2c_addr = 0x8;
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} else {
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i2c_bus = 4;
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break;
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i2c_addr = 0x18;
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}
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mtk_i2c_bus_init(i2c_bus);
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ps8640_init(i2c_bus, 0x18);
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if (ps8640_get_edid(i2c_bus, 0x18, &edid)) {
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ps8640_init(i2c_bus, i2c_addr);
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if (ps8640_get_edid(i2c_bus, i2c_addr, &edid)) {
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printk(BIOS_ERR, "Can't get panel's edid\n");
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return;
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}
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@ -22,7 +22,7 @@ static const struct mt8173_sdram_params sdram_configs[] = {
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#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0000 */
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#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0001 */
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#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 0010 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
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#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 0011 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */
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@ -0,0 +1,116 @@
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{ /* 2GB (8Gb + 8Gb) for single rank dram setting */
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{
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.impedance_drvp = 0x9,
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.impedance_drvn = 0xa,
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.datlat_ucfirst = 19,
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.ca_train = {
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[CHANNEL_A] = { 7, 7, 5, 6, 2, 1, 0, 1, 0, 2},
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[CHANNEL_B] = { 1, 2, 2, 0, 2, 3, 3, 3, 3, 3}
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},
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.ca_train_center = {
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[CHANNEL_A] = 2,
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[CHANNEL_B] = 0
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},
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.wr_level = {
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[CHANNEL_A] = { 5, 6, 5, 6},
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[CHANNEL_B] = { 6, 6, 6, 4}
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},
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.gating_win = {
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[CHANNEL_A] = {
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{ 28, 56},
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{ 28, 56}
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},
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[CHANNEL_B] = {
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{ 28, 56},
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{ 28, 56}
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}
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},
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.rx_dqs_dly = {
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[CHANNEL_A] = 0x110e0b0b,
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[CHANNEL_B] = 0x12100d0d
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},
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.rx_dq_dly = {
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[CHANNEL_A] = {
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0x01040302,
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0x04010300,
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0x02040300,
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0x04030302,
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0x04070400,
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0x07070707,
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0x05070808,
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0x00010404
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},
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[CHANNEL_B] = {
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0x05060604,
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0x04010400,
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0x05070300,
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0x05030504,
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0x07090500,
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0x08090707,
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0x080a0a0a,
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0x02000604
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}
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},
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},
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{
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.actim = 0xaafd478c,
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.actim1 = 0x91001f59,
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.actim05t = 0x000025e1,
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.conf1 = 0x00048403,
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.conf2 = 0x030000a9,
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.ddr2ctl = 0x000063b1,
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.gddr3ctl1 = 0x11000000,
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.misctl0 = 0x21000000,
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.pd_ctrl = 0xd1976442,
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.rkcfg = 0x002156c1,
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.test2_3 = 0xbfc70401,
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.test2_4 = 0x2801110d
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},
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{
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.cona = 0x50a350a7,
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.conb = 0x17283544,
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.conc = 0x0a1a0b1a,
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.cond = 0x00000000,
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.cone = 0xffff0848,
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.conf = 0x08420000,
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.cong = 0x2b2b2a38,
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.conh = 0x00000000,
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.conm_1 = 0x40000500,
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.conm_2 = 0x400005ff,
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.mdct_1 = 0x80030303,
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.mdct_2 = 0x34220c3f,
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.test0 = 0xcccccccc,
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.test1 = 0xcccccccc,
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.testb = 0x00060124,
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.testc = 0x38470000,
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.testd = 0x00000000,
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.arba = 0x7f077a49,
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.arbc = 0xa0a070dd,
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.arbd = 0x07007046,
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.arbe = 0x40407046,
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.arbf = 0xa0a070c6,
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.arbg = 0xffff7047,
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.arbi = 0x20406188,
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.arbj = 0x9719595e,
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.arbk = 0x64f3fc79,
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.slct_1 = 0x00010800,
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.slct_2 = 0xff03ff00,
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.bmen = 0x00ff0001
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},
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{
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.mrs_1 = 0x00830001,
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.mrs_2 = 0x001c0002,
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.mrs_3 = 0x00010003,
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.mrs_10 = 0x00ff000a,
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.mrs_11 = 0x0000000b,
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.mrs_63 = 0x0000003f
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},
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.type = TYPE_LPDDR3,
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.dram_freq = 896 * MHz,
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},
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