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google/oak: elm: Update the differences between oak-rev6 and elm-rev0 

- Remove the deprecated revison settings.
- Change LID pin to SPI_CK.
- Add i2c bus number and i2c slave address for elm.
- Skip the pin configurations(ALC5514 and USB OC pins) belonging to Oak.
- Add Hynix 4GB DRAM config

BRANCH=none
BUG=chrome-os-partner:51725
TEST=boot to kernel on elm-rev0

Change-Id: Ifaedd115c84d095ee289b576ff76af6b0aa3e545
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ed4543cdc7e84a0463b73dda96027270ec30272
Original-Change-Id: Id957374d7a67b8c72df1d07a6cecc1064d4e0356
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332733
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14692
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Yidi Lin 2016-03-16 16:59:17 +08:00 committed by Patrick Georgi
parent 9a57095bd2
commit 19318ddab5
5 changed files with 172 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/oak/Kconfig
View File

@ -83,6 +83,6 @@ config GBB_HWID
config BOARD_ID_ADJUSTMENT
int
default 0 if BOARD_GOOGLE_OAK
default 6
default 7
endif # BOARD_GOOGLE_OAK

5
src/mainboard/google/oak/gpio.h
View File

@ -17,8 +17,11 @@
#define __MAINBOARD_GOOGLE_OAK_GPIO_H__
#include <soc/pinmux.h>
#define LID ((board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7) ? \
PAD_EINT12 : PAD_SPI_CK)
enum {
LID = PAD_EINT12,
/* Board ID related GPIOS. */
BOARD_ID_0 = PAD_RDN3_A,
BOARD_ID_1 = PAD_RDP3_A,

65
src/mainboard/google/oak/mainboard.c
View File

@ -87,12 +87,23 @@ static void configure_audio(void)
gpio_set_mode(PAD_I2S0_MCK, PAD_I2S0_MCK_FUNC_I2S1_MCK);
gpio_set_mode(PAD_I2S0_DATA0, PAD_I2S0_DATA0_FUNC_I2S1_DO_1);
gpio_set_mode(PAD_I2S0_DATA1, PAD_I2S0_DATA1_FUNC_I2S2_DI_2);
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT >= 5)
gpio_set_mode(PAD_UCTS0, PAD_UCTS0_FUNC_I2S2_DI_1);
/* codec ext MCLK ON */
mt6391_gpio_output(MT6391_KP_COL4, 1);
switch (board_id() + CONFIG_BOARD_ID_ADJUSTMENT) {
case 2:
case 3:
case 4:
mt6391_gpio_output(MT6391_KP_COL5, 1);
break;
case 5:
case 6:
gpio_set_mode(PAD_UCTS0, PAD_UCTS0_FUNC_I2S2_DI_1);
mt6391_gpio_output(MT6391_KP_COL5, 1);
break;
default:
break;
}
/* Init i2c bus Timing register for audio codecs */
mtk_i2c_bus_init(CODEC_I2C_BUS);
@ -111,10 +122,13 @@ static void configure_usb(void)
/* Configure USB OC pins*/
gpio_input_pullup(PAD_MSDC3_DSL);
gpio_input_pullup(PAD_CMPCLK);
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7)
gpio_input_pullup(PAD_PCM_SYNC);
}
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4) {
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4 &&
board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7)
{
/* USB 2.0 type A port over current interrupt pin(low active) */
gpio_input_pullup(PAD_UCTS2);
/* USB 2.0 type A port BC1.2 STATUS(low active) */
@ -134,9 +148,6 @@ static void configure_backlight(void)
{
/* Configure PANEL_LCD_POWER_EN */
switch (board_id() + CONFIG_BOARD_ID_ADJUSTMENT) {
case 1:
case 2:
break;
case 3:
gpio_output(PAD_UCTS2, 0);
break;
@ -156,26 +167,6 @@ static void configure_display(void)
{
mtcmos_display_power_on();
switch (board_id() + CONFIG_BOARD_ID_ADJUSTMENT) {
case 0:
/* board from Rev0, Rev1 */
/* vgp2 set to 1.8V for it6151 */
mt6391_configure_ldo(LDO_VGP2, LDO_1P8);
gpio_output(PAD_PCM_RX, 0); /* IT6151_SYSRSTN */
gpio_output(PAD_CMMCLK, 1); /* PANEL_3V3_ENABLE */
gpio_output(PAD_PCM_SYNC, 1); /* IT6151_1V2_ENABLE */
gpio_output(PAD_PCM_RX, 1); /* IT6151_SYSRSTN */
break;
case 1:
/* board from Rev0, Rev1 */
/* vgp2 set to 1.8V for it6151 */
mt6391_configure_ldo(LDO_VGP2, LDO_1P8);
gpio_output(PAD_URTS0, 0); /* IT6151_SYSRSTN */
gpio_output(PAD_URTS2, 1); /* IT6151_1V2_ENABLE */
gpio_output(PAD_CMMCLK, 1); /* PANEL_3V3_ENABLE */
gpio_output(PAD_URTS0, 1); /* IT6151_SYSRSTN */
break;
default:
/* board from Rev2 */
gpio_output(PAD_CMMCLK, 1); /* PANEL_3V3_ENABLE */
/* vgp2 set to 3.3V for ps8640 */
@ -198,27 +189,25 @@ static void configure_display(void)
/* for level shift(1.8V to 3.3V) on */
udelay(100);
}
}
static void display_startup(void)
{
struct edid edid;
u8 i2c_bus;
u8 i2c_bus, i2c_addr;
int ret;
switch (board_id() + CONFIG_BOARD_ID_ADJUSTMENT) {
case 0:
case 1:
i2c_bus = 3;
break;
default:
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 6) {
i2c_bus = 0;
i2c_addr = 0x8;
} else {
i2c_bus = 4;
break;
i2c_addr = 0x18;
}
mtk_i2c_bus_init(i2c_bus);
ps8640_init(i2c_bus, 0x18);
if (ps8640_get_edid(i2c_bus, 0x18, &edid)) {
ps8640_init(i2c_bus, i2c_addr);
if (ps8640_get_edid(i2c_bus, i2c_addr, &edid)) {
printk(BIOS_ERR, "Can't get panel's edid\n");
return;
}

2
src/mainboard/google/oak/sdram_configs.c
View File

@ -22,7 +22,7 @@ static const struct mt8173_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0000 */
#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0001 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 0010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 0011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */

116
src/mainboard/google/oak/sdram_inf/sdram-lpddr3-hynix-4GB.inc Normal file
View File

@ -0,0 +1,116 @@
{ /* 2GB (8Gb + 8Gb) for single rank dram setting */
{
.impedance_drvp = 0x9,
.impedance_drvn = 0xa,
.datlat_ucfirst = 19,
.ca_train = {
[CHANNEL_A] = { 7, 7, 5, 6, 2, 1, 0, 1, 0, 2},
[CHANNEL_B] = { 1, 2, 2, 0, 2, 3, 3, 3, 3, 3}
},
.ca_train_center = {
[CHANNEL_A] = 2,
[CHANNEL_B] = 0
},
.wr_level = {
[CHANNEL_A] = { 5, 6, 5, 6},
[CHANNEL_B] = { 6, 6, 6, 4}
},
.gating_win = {
[CHANNEL_A] = {
{ 28, 56},
{ 28, 56}
},
[CHANNEL_B] = {
{ 28, 56},
{ 28, 56}
}
},
.rx_dqs_dly = {
[CHANNEL_A] = 0x110e0b0b,
[CHANNEL_B] = 0x12100d0d
},
.rx_dq_dly = {
[CHANNEL_A] = {
0x01040302,
0x04010300,
0x02040300,
0x04030302,
0x04070400,
0x07070707,
0x05070808,
0x00010404
},
[CHANNEL_B] = {
0x05060604,
0x04010400,
0x05070300,
0x05030504,
0x07090500,
0x08090707,
0x080a0a0a,
0x02000604
}
},
},
{
.actim = 0xaafd478c,
.actim1 = 0x91001f59,
.actim05t = 0x000025e1,
.conf1 = 0x00048403,
.conf2 = 0x030000a9,
.ddr2ctl = 0x000063b1,
.gddr3ctl1 = 0x11000000,
.misctl0 = 0x21000000,
.pd_ctrl = 0xd1976442,
.rkcfg = 0x002156c1,
.test2_3 = 0xbfc70401,
.test2_4 = 0x2801110d
},
{
.cona = 0x50a350a7,
.conb = 0x17283544,
.conc = 0x0a1a0b1a,
.cond = 0x00000000,
.cone = 0xffff0848,
.conf = 0x08420000,
.cong = 0x2b2b2a38,
.conh = 0x00000000,
.conm_1 = 0x40000500,
.conm_2 = 0x400005ff,
.mdct_1 = 0x80030303,
.mdct_2 = 0x34220c3f,
.test0 = 0xcccccccc,
.test1 = 0xcccccccc,
.testb = 0x00060124,
.testc = 0x38470000,
.testd = 0x00000000,
.arba = 0x7f077a49,
.arbc = 0xa0a070dd,
.arbd = 0x07007046,
.arbe = 0x40407046,
.arbf = 0xa0a070c6,
.arbg = 0xffff7047,
.arbi = 0x20406188,
.arbj = 0x9719595e,
.arbk = 0x64f3fc79,
.slct_1 = 0x00010800,
.slct_2 = 0xff03ff00,
.bmen = 0x00ff0001
},
{
.mrs_1 = 0x00830001,
.mrs_2 = 0x001c0002,
.mrs_3 = 0x00010003,
.mrs_10 = 0x00ff000a,
.mrs_11 = 0x0000000b,
.mrs_63 = 0x0000003f
},
.type = TYPE_LPDDR3,
.dram_freq = 896 * MHz,
},