Inagua: mainboard specific GPIO setting
Pcie device connected to Hudson/sb800 southbridge GPP training can works, by applying this mainbaind specific GPIO PCIE De-Assert setting. Change-Id: I563b2e6354a958a28f5d0162e7a4d60aa437fb9b Signed-off-by: Kerry Sheh <shekairui@gmail.com> Signed-off-by: Kerry Sheh <kerry.she@amd.com> Reviewed-on: http://review.coreboot.org/543 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
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@ -26,6 +26,7 @@
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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//#include <southbridge/amd/sb800/sb800.h>
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#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
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#include "chip.h"
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void set_pcie_reset(void);
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@ -40,11 +41,34 @@ void set_pcie_reset(void)
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}
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/**
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* TODO
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* mainboard specific SB CIMx callback
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*/
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void set_pcie_dereset(void)
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{
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/**
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* GPIO32 Pcie Device DeAssert for APU
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* GPIO25 Pcie LAN, APU GPP2
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* GPIO02 MINIPCIE SLOT1, APU GPP3
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* GPIO50 Pcie Device DeAssert for Hudson Southbridge
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* GPIO05 Express Card, SB GPP0
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* GPIO26 NEC USB3.0GPPUSB, SB GPP1
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* GPIO00 MINIPCIE SLOT2, SB GPP2
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* GPIO05 Pcie X1 Slot, SB GPP3
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*/
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/* Multi-function pins switch to GPIO0-35, these pins are shared with
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* PCI pins, make sure Husson PCI device is disabled.
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*/
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RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
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/* select IOMux to function1/2, corresponds to GPIO */
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RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG32, AccWidthUint8, ~(BIT0 | BIT1), 1);
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RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG50, AccWidthUint8, ~(BIT0 | BIT1), 2);
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/* output low */
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RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG32, AccWidthUint8, ~(0xFF), 0x48);
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RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG50, AccWidthUint8, ~(0xFF), 0x48);
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}
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uint64_t uma_memory_base, uma_memory_size;
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@ -95,6 +119,8 @@ static void inagua_enable(device_t dev)
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uma_memory_base = 0x30000000; /* 1GB system memory supported */
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#endif
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/* Inagua mainboard specific setting */
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set_pcie_dereset();
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}
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int add_mainboard_resources(struct lb_memory *mem)
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