From 193aac88353574e5ab9de5fd50d240ae8249c155 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 18 Jan 2021 19:50:26 +0100 Subject: [PATCH] cpu/x86/sipi_vector.S: Fix reading MCU revision MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Writing 0 to MSR IA32_BIOS_SIGN_ID before fetching this MSRs content is required. This is how things are done in cpu/intel/microcode/microcode.c. The "Intel® 64 and IA-32 Architectures Software Developer’s Manual" also recommends this: "It is recommended that this field be preloaded with 0 prior to executing CPUID" (this field being %edx). Change-Id: I24a87aff9a699ed8ab2598007c8b8562d0555ac5 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/49670 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Zhang Reviewed-by: Angel Pons Reviewed-by: Subrata Banik Reviewed-by: Patrick Rudolph --- src/cpu/x86/sipi_vector.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index e1b90890ed..f9b29576bd 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -115,6 +115,10 @@ _start: jz microcode_done /* Bypass if no microde exists. */ /* Get the Microcode version. */ + xorl %eax, %eax + xorl %edx, %edx + movl $IA32_BIOS_SIGN_ID, %ecx + wrmsr mov $1, %eax cpuid mov $IA32_BIOS_SIGN_ID, %ecx