soc/intel/common: Fix bugs for GPIO_LOCK_UNLOCK

Per the Intel External Design Specification (doc #618876), the opcode
for GPIO_LOCK_UNLOCK is 0x13.  This commit fixes a bug where the opcode
was defined as 13 decimal instead of hexadecimal.  Additionally, it
fixes another issue where the `pcr_execute_sideband_msg()` function
doesn't actually write the data when this opcode is selected.

BUG=b:191189275
BRANCH=None
TEST=With additional code that uses this opcode, verify that the lock
functionality works by locking a pad in firmware and attempting to
modify the configuration of the pad from the OS.

Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Ie14fff595474cdfd647c2b36f1eeb5e018f67375
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55556
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/common/block/include/intelblocks/pcr.h

@@ -27,13 +27,13 @@ void pcr_or8(uint8_t pid, uint16_t offset, uint8_t ordata);
 
 /* SBI command */
 enum {
-	MEM_READ = 0,
-	MEM_WRITE = 1,
-	PCI_CONFIG_READ = 4,
-	PCI_CONFIG_WRITE = 5,
-	PCR_READ = 6,
-	PCR_WRITE = 7,
-	GPIO_LOCK_UNLOCK = 13,
+	MEM_READ = 0x00,
+	MEM_WRITE = 0x01,
+	PCI_CONFIG_READ = 0x04,
+	PCI_CONFIG_WRITE = 0x05,
+	PCR_READ = 0x06,
+	PCR_WRITE = 0x07,
+	GPIO_LOCK_UNLOCK = 0x13,
 };
 
 struct pcr_sbi_msg {

src/soc/intel/common/block/pcr/pcr.c

@@ -330,6 +330,7 @@ int pcr_execute_sideband_msg(struct pcr_sbi_msg *msg, uint32_t *data,
 		case MEM_WRITE:
 		case PCI_CONFIG_WRITE:
 		case PCR_WRITE:
+		case GPIO_LOCK_UNLOCK:
 			/*
 			 * 6. Write P2SB PCI offset D4h[31:0] with the
 			 * intended data accordingly