soc/intel/common: Fix bugs for GPIO_LOCK_UNLOCK
Per the Intel External Design Specification (doc #618876), the opcode for GPIO_LOCK_UNLOCK is 0x13. This commit fixes a bug where the opcode was defined as 13 decimal instead of hexadecimal. Additionally, it fixes another issue where the `pcr_execute_sideband_msg()` function doesn't actually write the data when this opcode is selected. BUG=b:191189275 BRANCH=None TEST=With additional code that uses this opcode, verify that the lock functionality works by locking a pad in firmware and attempting to modify the configuration of the pad from the OS. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Ie14fff595474cdfd647c2b36f1eeb5e018f67375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55556 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -27,13 +27,13 @@ void pcr_or8(uint8_t pid, uint16_t offset, uint8_t ordata);
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/* SBI command */
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/* SBI command */
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enum {
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enum {
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MEM_READ = 0,
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MEM_READ = 0x00,
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MEM_WRITE = 1,
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MEM_WRITE = 0x01,
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PCI_CONFIG_READ = 4,
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PCI_CONFIG_READ = 0x04,
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PCI_CONFIG_WRITE = 5,
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PCI_CONFIG_WRITE = 0x05,
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PCR_READ = 6,
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PCR_READ = 0x06,
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PCR_WRITE = 7,
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PCR_WRITE = 0x07,
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GPIO_LOCK_UNLOCK = 13,
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GPIO_LOCK_UNLOCK = 0x13,
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};
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};
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struct pcr_sbi_msg {
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struct pcr_sbi_msg {
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@ -330,6 +330,7 @@ int pcr_execute_sideband_msg(struct pcr_sbi_msg *msg, uint32_t *data,
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case MEM_WRITE:
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case MEM_WRITE:
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case PCI_CONFIG_WRITE:
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case PCI_CONFIG_WRITE:
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case PCR_WRITE:
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case PCR_WRITE:
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case GPIO_LOCK_UNLOCK:
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/*
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/*
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* 6. Write P2SB PCI offset D4h[31:0] with the
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* 6. Write P2SB PCI offset D4h[31:0] with the
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* intended data accordingly
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* intended data accordingly
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