- Sync up northbridge/amd/amdk8
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
parent
5d7dafea86
commit
1944680bfd
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@ -17,7 +17,8 @@ static int enumerate_ht_chain(void)
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/* If the chain is enumerated quit */
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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(((id >> 16) & 0xffff) == 0x0000))
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{
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break;
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}
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hdr_type = pci_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE);
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@ -25,7 +26,8 @@ static int enumerate_ht_chain(void)
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hdr_type &= 0x7f;
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if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
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(hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
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(hdr_type == PCI_HEADER_TYPE_BRIDGE))
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{
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pos = pci_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST);
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}
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while(pos != 0) {
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@ -42,7 +42,7 @@ static void mcf3_read_resources(device_t dev)
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pci_dev_read_resources(dev);
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/* If we are not the first processor don't allocate the gart apeture */
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if (dev->path.u.pci.devfn != PCI_DEVFN(0x18, 0x3)) {
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if (dev->path.u.pci.devfn != PCI_DEVFN(0x18, 3)) {
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return;
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}
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@ -68,19 +68,20 @@ static void set_agp_aperture(device_t dev)
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if (resource) {
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device_t pdev;
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uint32_t gart_base, gart_acr;
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/* Remember this resource has been stored */
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resource->flags |= IORESOURCE_STORED;
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/*Find the size of the GART aperture */
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gart_acr = (0<<6)|(0<<5)|(0<<4)| ((log2(resource->size) - 25) << 1)|(0<<0);
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/* Find the size of the GART aperture */
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gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
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/* Get the base address */
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gart_base = ((resource->base) >> 25) & 0x00007fff;
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/* Update the other northbriges */
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pdev = 0;
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while (pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev)) {
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/* Store GART size but don't enable it */
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while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
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/* Store the GART size but don't enable it */
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pci_write_config32(pdev, 0x90, gart_acr);
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/* Store the GART base address */
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@ -175,8 +176,6 @@ static void misc_control_init(struct device *dev)
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needs_reset = 1; /* Needed? */
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}
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}
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#if CONFIG_MAX_CPUS > 1
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/* Single CPU systems don't seem to need this. It might cause resets? (YhLu) */
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/* Optimize the Link read pointers */
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f0_dev = dev_find_slot(0, dev->path.u.pci.devfn - 3);
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if (f0_dev) {
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@ -202,7 +201,6 @@ static void misc_control_init(struct device *dev)
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else {
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printk_err("Missing f0 device!\n");
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}
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#endif
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if (needs_reset) {
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printk_debug("resetting cpu\n");
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hard_reset();
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@ -217,6 +215,7 @@ static struct device_operations mcf3_ops = {
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.enable_resources = pci_dev_enable_resources,
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.init = misc_control_init,
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.scan_bus = 0,
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.ops_pci = 0,
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};
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static struct pci_driver mcf3_driver __pci_driver = {
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@ -1,20 +1,20 @@
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#include <cpu/k8/mtrr.h>
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#include <cpu/x86/mem.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/mtrr.h>
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#include "raminit.h"
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#include "amdk8.h"
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#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
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# error "CONFIG_LB_MEM_TOPK must be a power of 2"
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#endif
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static void setup_resource_map(const unsigned int *register_values, int max)
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{
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int i;
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print_debug("setting up resource map....");
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#if 0
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print_debug("\r\n");
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#endif
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for (i = 0; i < max; i += 3) {
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for(i = 0; i < max; i += 3) {
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device_t dev;
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unsigned where;
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unsigned long reg;
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@ -1921,11 +1921,21 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct
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return dimm_mask;
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}
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static int controller_present(const struct mem_controller *ctrl)
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{
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return pci_read_config32(ctrl->f0, 0) == 0x11001022;
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}
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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{
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struct spd_set_memclk_result result;
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const struct mem_param *param;
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long dimm_mask;
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#if 1
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if (!controller_present(ctrl)) {
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print_debug("No memory controller present\r\n");
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return;
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}
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#endif
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hw_enable_ecc(ctrl);
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activate_spd_rom(ctrl);
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dimm_mask = spd_detect_dimms(ctrl);
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@ -1972,6 +1982,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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/* Before enabling memory start the memory clocks */
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for(i = 0; i < controllers; i++) {
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uint32_t dch;
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if (!controller_present(ctrl + i))
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continue;
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dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
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if (dch & (DCH_MEMCLK_EN0|DCH_MEMCLK_EN1|DCH_MEMCLK_EN2|DCH_MEMCLK_EN3)) {
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dch |= DCH_MEMCLK_VALID;
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@ -1991,6 +2003,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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for(i = 0; i < controllers; i++) {
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uint32_t dcl, dch;
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if (!controller_present(ctrl + i))
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continue;
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/* Skip everything if I don't have any memory on this controller */
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dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
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if (!(dch & DCH_MEMCLK_VALID)) {
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@ -2021,6 +2035,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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}
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for(i = 0; i < controllers; i++) {
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uint32_t dcl, dch;
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if (!controller_present(ctrl + i))
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continue;
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/* Skip everything if I don't have any memory on this controller */
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dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
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if (!(dch & DCH_MEMCLK_VALID)) {
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@ -2058,78 +2074,16 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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/* Save the value of msr_201 */
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msr_201 = rdmsr(0x201);
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print_debug("Clearing LinuxBIOS memory: ");
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print_debug("Clearing initial memory region: ");
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/* disable cache */
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__asm__ volatile(
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"movl %%cr0, %0\n\t"
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"orl $0x40000000, %0\n\t"
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"movl %0, %%cr0\n\t"
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:"=r" (cnt)
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);
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/* Disable fixed mtrrs */
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msr = rdmsr(MTRRdefType_MSR);
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msr.lo &= ~(1<<10);
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wrmsr(MTRRdefType_MSR, msr);
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/* Set the variable mtrrs to write combine */
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msr.hi = 0;
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msr.lo = 0 | MTRR_TYPE_WRCOMB;
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wrmsr(0x200, msr);
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/* Set the limit to 1M of ram */
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msr.hi = 0x000000ff;
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msr.lo = (~((CONFIG_LB_MEM_TOPK << 10) - 1)) | 0x800;
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wrmsr(0x201, msr);
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/* enable cache */
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__asm__ volatile(
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"movl %%cr0, %0\n\t"
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"andl $0x9fffffff, %0\n\t"
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"movl %0, %%cr0\n\t"
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:"=r" (cnt)
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);
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/* Use write combine caching while we setup the first 1M */
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cache_lbmem(MTRR_TYPE_WRCOMB);
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/* clear memory 1meg */
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__asm__ volatile(
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"1: \n\t"
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"movl %0, %%fs:(%1)\n\t"
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"addl $4,%1\n\t"
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"subl $4,%2\n\t"
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"jnz 1b\n\t"
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:
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: "a" (0), "D" (0), "c" (1024*1024)
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);
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clear_memory((void *)0, CONFIG_LB_MEM_TOPK << 10);
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/* disable cache */
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__asm__ volatile(
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"movl %%cr0, %0\n\t"
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"orl $0x40000000, %0\n\t"
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"movl %0, %%cr0\n\t"
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:"=r" (cnt)
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);
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/* restore msr registers */
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msr = rdmsr(MTRRdefType_MSR);
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msr.lo |= 0x0400;
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wrmsr(MTRRdefType_MSR, msr);
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/* Restore the variable mtrrs */
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msr.hi = 0;
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msr.lo = MTRR_TYPE_WRBACK;
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wrmsr(0x200, msr);
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wrmsr(0x201, msr_201);
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/* enable cache */
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__asm__ volatile(
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"movl %%cr0, %0\n\t"
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"andl $0x9fffffff, %0\n\t"
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"movl %0, %%cr0\n\t"
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:"=r" (cnt)
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);
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/* The first 1M is now setup, use it */
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cache_lbmem(MTRR_TYPE_WRBACK);
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print_debug(" done\r\n");
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}
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