mb/google/mancomb: Add smihandler

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I52411917d9e7e8f8d9ac5d1c9b426a58ba09f5ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
This commit is contained in:
Eric Lai 2021-03-18 16:30:09 +08:00 committed by Raul Rangel
parent 87e27e1d0e
commit 1954c1f92e
5 changed files with 53 additions and 0 deletions

View file

@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_16384
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI
select ELOG
select ELOG_GSMI
select HAVE_ACPI_RESUME
select MAINBOARD_HAS_CHROMEOS
select SOC_AMD_CEZANNE

View file

@ -0,0 +1,36 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
#include <cpu/x86/smm.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/smm.h>
#include <elog.h>
#include <variant/ec.h>
void mainboard_smi_gpi(u32 gpi_sts)
{
chromeec_smi_process_events();
}
void mainboard_smi_sleep(u8 slp_typ)
{
size_t num_gpios;
const struct soc_amd_gpio *gpios;
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
gpios = variant_sleep_gpio_table(&num_gpios);
program_gpios(gpios, num_gpios);
}
int mainboard_smi_apmc(u8 apmc)
{
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
return 0;
}
void elog_gsmi_cb_mainboard_log_wake_source(void)
{
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS);
}

View file

@ -3,3 +3,5 @@ bootblock-y += gpio.c
ramstage-y += gpio.c
verstage-y += gpio.c
smm-y += gpio.c

View file

@ -168,6 +168,11 @@ static const struct soc_amd_gpio early_gpio_table[] = {
PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE),
};
/* GPIO configuration for sleep */
static const struct soc_amd_gpio sleep_gpio_table[] = {
/* TODO: Fill sleep gpio configuration */
};
const struct soc_amd_gpio *__weak variant_base_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(base_gpio_table);
@ -183,3 +188,8 @@ const struct soc_amd_gpio *__weak variant_early_gpio_table(size_t *size)
*size = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(sleep_gpio_table);
return sleep_gpio_table;
}

View file

@ -21,4 +21,7 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size);
/* This function provides early GPIO init in bootblock or psp. */
const struct soc_amd_gpio *variant_early_gpio_table(size_t *size);
/* This function provides GPIO settings before entering sleep. */
const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size);
#endif /* __BASEBOARD_VARIANTS_H__ */