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soc/intel/apollolake/acpi: Tidy the PCI Memory Region 

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8997f9c111142a908b60675023d1a7dd86d3632a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66238
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2022-07-28 21:35:35 +01:00
parent de19bc372b
commit 197cfe03d5
1 changed files with 6 additions and 3 deletions
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9
src/soc/intel/apollolake/acpi/northbridge.asl
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@ -72,11 +72,14 @@ Method (_CRS, 0, Serialized)
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000,,, PM01) 0x00000000,,, PM01)
/* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ /*
* PCI Memory Region above 4 GiB
* (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE))
*/
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
NonCacheable, ReadWrite, NonCacheable, ReadWrite,
0x00000000, 0x10000, 0x1ffff, 0x00000000, 0x00000000, 0x00010000, 0x0001ffff, 0x00000000,
0x10000,,, PM02) 0x00010000,,, PM02)
}) })
/* Find PCI resource area in MCRS */ /* Find PCI resource area in MCRS */