create some technologic systems ts530 infrastructure
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
40ab2d1213
commit
198409afe0
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extern struct chip_control mainboard_technologic_ts5300_control;
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struct mainboard_technologic_ts5300_config {
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int nothing;
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};
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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420 4 e 7 boot_second
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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1008 16 h 0 check_sum
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Network
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7 1 HDD
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7 2 Floppy
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7 8 Fallback_Network
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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checksums
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checksum 392 1007 1008
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static void print_debug_pci_dev(unsigned dev)
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{
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print_debug("PCI: ");
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print_debug_hex8((dev >> 16) & 0xff);
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print_debug_char(':');
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print_debug_hex8((dev >> 11) & 0x1f);
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print_debug_char('.');
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print_debug_hex8((dev >> 8) & 7);
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}
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static void print_pci_devices(void)
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{
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device_t dev;
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for(dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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print_debug_pci_dev(dev);
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print_debug("\r\n");
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}
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}
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static void dump_pci_device(unsigned dev)
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{
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int i;
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print_debug_pci_dev(dev);
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print_debug("\r\n");
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for(i = 0; i <= 255; i++) {
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unsigned char val;
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if ((i & 0x0f) == 0) {
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print_debug_hex8(i);
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print_debug_char(':');
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}
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val = pci_read_config8(dev, i);
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print_debug_char(' ');
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print_debug_hex8(val);
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if ((i & 0x0f) == 0x0f) {
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print_debug("\r\n");
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}
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}
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}
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static void dump_pci_devices(void)
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{
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device_t dev;
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for(dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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dump_pci_device(dev);
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}
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}
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#if 0
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static void dump_spd_registers(const struct mem_controller *ctrl)
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{
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int i;
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print_debug("\r\n");
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for(i = 0; i < 4; i++) {
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unsigned device;
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device = ctrl->channel0[i];
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if (device) {
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int j;
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print_debug("dimm: ");
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print_debug_hex8(i);
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print_debug(".0: ");
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print_debug_hex8(device);
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for(j = 0; j < 256; j++) {
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0) {
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print_debug("\r\n");
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print_debug_hex8(j);
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print_debug(": ");
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}
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status = smbus_read_byte(device, j);
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if (status < 0) {
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print_debug("bad device\r\n");
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break;
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}
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byte = status & 0xff;
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print_debug_hex8(byte);
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print_debug_char(' ');
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}
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print_debug("\r\n");
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}
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device = ctrl->channel1[i];
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if (device) {
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int j;
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print_debug("dimm: ");
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print_debug_hex8(i);
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print_debug(".1: ");
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print_debug_hex8(device);
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for(j = 0; j < 256; j++) {
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0) {
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print_debug("\r\n");
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print_debug_hex8(j);
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print_debug(": ");
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}
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status = smbus_read_byte(device, j);
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if (status < 0) {
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print_debug("bad device\r\n");
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break;
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}
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byte = status & 0xff;
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print_debug_hex8(byte);
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print_debug_char(' ');
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}
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print_debug("\r\n");
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}
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}
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}
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#endif
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include "arch/romcc_io.h"
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#include "pc80/mc146818rtc_early.c"
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#include "cpu/p6/boot_cpu.c"
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static void main(void)
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{
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/* for now, just always assume failure */
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#if 0
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/* Is this a cpu reset? */
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if (cpu_init_detected()) {
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if (last_boot_normal()) {
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asm("jmp __normal_image");
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} else {
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asm("jmp __cpu_reset");
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}
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}
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/* This is the primary cpu how should I boot? */
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else if (do_normal_boot()) {
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asm("jmp __normal_image");
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}
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#endif
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}
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// This pirq table is dummy and only here for existance.
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// It MUST be replaced as soon as LinuxBIOS is operable on this board.
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*5, /* there can be total 5 devices on the bus */
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0, /* Where the interrupt router lies (bus) */
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0x88, /* Where the interrupt router lies (dev) */
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0x1c20, /* IRQs devoted exclusively to PCI usage */
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0x1106, /* Vendor */
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0x8231, /* Device */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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/* 8231 ethernet */
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{0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0},
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/* 8231 internal */
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{0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
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/* PCI slot */
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{0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0},
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{0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0},
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{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
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}
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};
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include <device/chip.h>
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#include "chip.h"
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static int
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mainboard_scan_bus(device_t root, int maxbus)
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{
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int retval;
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printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
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retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
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printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
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return maxbus;
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}
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static struct device_operations mainboard_operations = {
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.read_resources = root_dev_read_resources,
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.set_resources = root_dev_set_resources,
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.enable_resources = enable_childrens_resources,
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.init = 0,
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.scan_bus = mainboard_scan_bus,
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.enable = 0,
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};
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static void enumerate(struct chip *chip)
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{
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struct chip *child;
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dev_root.ops = &mainboard_operations;
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chip->dev = &dev_root;
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chip->bus = 0;
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for(child = chip->children; child; child = child->next) {
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child->bus = &dev_root.link[0];
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}
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}
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struct chip_control mainboard_technologic_ts5300_control = {
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.enumerate = enumerate,
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.name = "Technologic Systems TS5300 mainboard ",
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};
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#if 0
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//#include "arch/romcc_io.h"
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#include <arch/io.h>
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typedef unsigned device_t;
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#define PCI_DEV(BUS, DEV, FN) ( \
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(((BUS) & 0xFF) << 16) | \
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(((DEV) & 0x1f) << 11) | \
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(((FN) & 0x7) << 8))
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static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
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{
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unsigned addr;
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addr = dev | where;
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outl(0x80000000 | (addr & ~3), 0xCF8);
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outb(value, 0xCFC + (addr & 3));
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}
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static void pci_write_config32(device_t dev, unsigned where, unsigned value)
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{
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unsigned addr;
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addr = dev | where;
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outl(0x80000000 | (addr & ~3), 0xCF8);
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outl(value, 0xCFC);
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}
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static unsigned pci_read_config32(device_t dev, unsigned where)
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{
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unsigned addr;
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addr = dev | where;
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outl(0x80000000 | (addr & ~3), 0xCF8);
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return inl(0xCFC);
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}
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#include "../../../northbridge/amd/amdk8/reset_test.c"
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void hard_reset(void)
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{
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set_bios_reset();
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pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
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}
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#endif
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