nb/intel/x4x: Clarify the raminit memory mapping
This replaces magic values by macros and adds some comments to improve readability. Adds a convenient function to fetch the test address of a rank. Also fixes the temporary memory map by changing a write to MCHBAR 0x100 to 0x110, since this is what vendor does. (No difference observed thus far) TESTED on DG43GT Change-Id: I58923e4a8a756f4ae65f759e7d46e03fad39fab7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
This commit is contained in:
Arthur Heymans
Patrick Georgi
parent
0bf87de667
commit
1994e448be
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@ -14,6 +14,7 @@
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <stdint.h>
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#include <arch/io.h>
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#include <arch/cpu.h>
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@ -974,9 +975,79 @@ static void odt_ddr2(struct sysinfo *s)
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}
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}
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static void pre_jedec_memory_map(void)
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{
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/*
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* Configure the memory mapping in stacked mode (channel 1 being mapped
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* above channel 0) and with 128M per rank.
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* This simplifies dram trainings a lot since those need a test address.
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*
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* +-------------+ => 0
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* | ch 0, rank 0|
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* +-------------+ => 0x8000000 (128M)
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* | ch 0, rank 1|
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* +-------------+ => 0x10000000 (256M)
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* | ch 0, rank 2|
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* +-------------+ => 0x18000000 (384M)
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* | ch 0, rank 3|
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* +-------------+ => 0x20000000 (512M)
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* | ch 1, rank 0|
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* +-------------+ => 0x28000000 (640M)
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* | ch 1, rank 1|
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* +-------------+ => 0x30000000 (768M)
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* | ch 1, rank 2|
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* +-------------+ => 0x38000000 (896M)
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* | ch 1, rank 3|
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* +-------------+
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*
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* After all trainings are done this is set to the real values specified
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* by the SPD.
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*/
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/* Set rank 0-3 populated */
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MCHBAR32(C0CKECTRL) = (MCHBAR32(C0CKECTRL) & ~1) | 0xf00000;
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MCHBAR32(C1CKECTRL) = (MCHBAR32(C1CKECTRL) & ~1) | 0xf00000;
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/* Set size of each rank to 128M */
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MCHBAR16(C0DRA01) = 0x0101;
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MCHBAR16(C0DRA23) = 0x0101;
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MCHBAR16(C1DRA01) = 0x0101;
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MCHBAR16(C1DRA23) = 0x0101;
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MCHBAR16(C0DRB0) = 0x0002;
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MCHBAR16(C0DRB1) = 0x0004;
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MCHBAR16(C0DRB2) = 0x0006;
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MCHBAR16(C0DRB3) = 0x0008;
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MCHBAR16(C1DRB0) = 0x0002;
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MCHBAR16(C1DRB1) = 0x0004;
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MCHBAR16(C1DRB2) = 0x0006;
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/*
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* For some reason the boundary needs to be 0x10 instead of 0x8 here.
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* Vendor does this too...
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*/
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MCHBAR16(C1DRB3) = 0x0010;
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MCHBAR8(0x111) = MCHBAR8(0x111) | STACKED_MEM;
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MCHBAR32(0x104) = 0;
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MCHBAR16(0x102) = 0x400;
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MCHBAR8(0x110) = (2 << 5) | (3 << 3);
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MCHBAR16(0x10e) = 0;
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MCHBAR32(0x108) = 0;
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pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOLUD, 0x4000);
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/* TOM(64M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */
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pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOM, 0x10);
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/* TOUUD(1M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */
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pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOUUD, 0x0400);
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pci_write_config32(PCI_DEV(0, 0, 0), D0F0_GBSM, 0x40000000);
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pci_write_config32(PCI_DEV(0, 0, 0), D0F0_BGSM, 0x40000000);
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pci_write_config32(PCI_DEV(0, 0, 0), D0F0_TSEG, 0x40000000);
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}
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u32 test_address(int channel, int rank)
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{
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ASSERT(channel <= 1 && rank < 4);
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return channel * 512 * MiB + rank * 128 * MiB;
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}
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static void dojedec_ddr2(u8 r, u8 ch, u8 cmd, u16 val)
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{
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u32 addr = (ch << 29) | (r*0x08000000);
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u32 addr = test_address(ch, r);
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volatile u32 rubbish;
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MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | cmd;
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@ -1046,7 +1117,7 @@ static void jedec_ddr2(struct sysinfo *s)
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default:
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break;
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}
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dojedec_ddr2(r + ch*4, ch, jedec[i][0], v);
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dojedec_ddr2(r, ch, jedec[i][0], v);
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udelay(1);
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printk(RAM_SPEW, "Jedec step %d\n", i);
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}
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@ -1516,27 +1587,7 @@ void raminit_ddr2(struct sysinfo *s, int fast_boot)
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printk(BIOS_DEBUG, "Done RCOMP update\n");
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}
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// Set defaults
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MCHBAR32(0x260) = (MCHBAR32(0x260) & ~1) | 0xf00000;
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MCHBAR32(0x660) = (MCHBAR32(0x660) & ~1) | 0xf00000;
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MCHBAR32(0x208) = 0x01010101;
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MCHBAR32(0x608) = 0x01010101;
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MCHBAR32(0x200) = 0x00040002;
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MCHBAR32(0x204) = 0x00080006;
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MCHBAR32(0x600) = 0x00040002;
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MCHBAR32(0x604) = 0x00100006;
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MCHBAR8(0x111) = MCHBAR8(0x111) | 0x2;
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MCHBAR32(0x104) = 0;
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MCHBAR16(0x102) = 0x400;
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MCHBAR8(0x100) = (2 << 5) | (3 << 3);
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MCHBAR16(0x10e) = 0;
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MCHBAR32(0x108) = 0;
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pci_write_config16(PCI_DEV(0, 0, 0), 0xb0, 0x4000);
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pci_write_config16(PCI_DEV(0, 0, 0), 0xa0, 0x0010);
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pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, 0x0400);
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pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, 0x40000000);
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pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, 0x40000000);
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pci_write_config32(PCI_DEV(0, 0, 0), 0xac, 0x40000000);
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pre_jedec_memory_map();
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// IOBUFACT
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if (CHANNEL_IS_POPULATED(s->dimms, 0)) {
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@ -1613,7 +1664,7 @@ void raminit_ddr2(struct sysinfo *s, int fast_boot)
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volatile u32 data;
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FOR_EACH_POPULATED_RANK(s->dimms, ch, r) {
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for (bank = 0; bank < 4; bank++) {
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reg32 = (ch << 29) | (r*0x8000000) |
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reg32 = test_address(ch, r) |
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(bank << 12);
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write32((u32 *)reg32, 0xffffffff);
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data = read32((u32 *)reg32);
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@ -306,9 +306,13 @@ static int calibrate_receive_enable(u8 channel, u8 lane,
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void rcven(struct sysinfo *s)
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{
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int i;
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int rank;
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u8 channel, lane, reg8;
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u32 addr;
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/*
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* Using the macros below the compiler warns about this possibly being
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* unitialised.
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*/
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u32 addr = 0;
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struct rec_timing timing[8];
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u8 mincoarse;
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@ -316,11 +320,15 @@ void rcven(struct sysinfo *s)
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MCHBAR8(0x9d8) = MCHBAR8(0x9d8) & ~0xc;
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MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80;
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FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) {
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addr = (channel << 29);
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mincoarse = 0xff;
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for (i = 0; i < RANKS_PER_CHANNEL &&
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!RANK_IS_POPULATED(s->dimms, channel, i); i++)
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addr += 128 * MiB;
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/*
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* Receive enable calibration happens on the first populated
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* rank on each channel.
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*/
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FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, channel, rank) {
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addr = test_address(channel, rank);
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break;
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}
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for (lane = 0; lane < 8; lane++) {
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printk(BIOS_DEBUG, "Channel %d, Lane %d addr=0x%08x\n",
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channel, lane, addr);
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@ -86,6 +86,25 @@
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#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
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#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
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#define CHDECMISC 0x111
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#define STACKED_MEM (1 << 1)
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#define C0DRB0 0x200
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#define C0DRB1 0x202
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#define C0DRB2 0x204
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#define C0DRB3 0x206
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#define C0DRA01 0x208
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#define C0DRA23 0x20a
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#define C0CKECTRL 0x260
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#define C1DRB0 0x600
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#define C1DRB1 0x602
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#define C1DRB2 0x604
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#define C1DRB3 0x606
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#define C1DRA01 0x608
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#define C1DRA23 0x60a
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#define C1CKECTRL 0x660
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#define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */
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#define PMSTS_WARM_RESET (1 << 8)
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#define PMSTS_BOTH_SELFREFRESH (3 << 0)
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@ -341,6 +360,7 @@ void raminit_ddr2(struct sysinfo *s, int fast_boot);
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void rcven(struct sysinfo *s);
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u32 fsb2mhz(u32 speed);
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u32 ddr2mhz(u32 speed);
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u32 test_address(int channel, int rank);
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extern const struct dll_setting default_ddr2_667_ctrl[7];
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extern const struct dll_setting default_ddr2_800_ctrl[7];
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