It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons.
Also it enables the FID/VID changes in SB. Jakllsch had some troubles with that too but on am2 CPU. Those bits are only documented in SB600. They arent in RRG RPR and BDG. Signed-off-by: Rudolf Marek <r.marek@asssembler.cz> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek
Rudolf Marek
parent
ed1d116e62
commit
199c694f49
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@ -30,10 +30,9 @@
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#include <cpu/amd/amdk8_sysconf.h>
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#include <arch/cpu.h>
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#if CONFIG_K8_REV_F_SUPPORT
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static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid,
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u8 *pstate_fid, u32 *pstate_power, int coreID,
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u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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u32 pcontrol_blk, u8 plen, u8 onlyBSP, u32 control)
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{
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int lenp, lenpr, i;
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@ -50,16 +49,8 @@ static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid
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lenp = acpigen_write_package(pstate_num);
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for (i = 0;i < pstate_num;i++) {
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u32 control, status;
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control =
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(0x3 << 30) | /* IRT */
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(0x2 << 28) | /* RVO */
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(0x1 << 27) | /* ExtType */
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(0x2 << 20) | /* PLL_LOCK_TIME */
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(0x0 << 18) | /* MVS */
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(0x5 << 11) | /* VST */
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(pstate_vid[i] << 6) |
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u32 status, c2;
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c2 = control | (pstate_vid[i] << 6) |
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pstate_fid[i];
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status =
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(pstate_vid[i] << 6) |
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@ -69,7 +60,7 @@ static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid
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pstate_power[i],
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0x64,
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0x7,
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control,
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c2,
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status);
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}
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/* update the package size */
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@ -81,6 +72,8 @@ static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid
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acpigen_patch_len(lenpr - 2);
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return lenpr;
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}
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#if CONFIG_K8_REV_F_SUPPORT
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/*
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* Details about this algorithm , refert to BDKG 10.5.1
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* Two parts are included, the another is the DSDT reconstruction process
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@ -90,7 +83,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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{
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int len;
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u8 processor_brand[49];
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u32 *v;
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u32 *v, control;
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struct cpuid_result cpuid1;
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struct power_limit_encoding {
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@ -367,15 +360,288 @@ write_pstates:
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len = 0;
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control = (0x3 << 30) | /* IRT */
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(0x2 << 28) | /* RVO */
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(0x1 << 27) | /* ExtType */
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(0x2 << 20) | /* PLL_LOCK_TIME */
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(0x0 << 18) | /* MVS */
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(0x5 << 11); /* VST */
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for (index = 0; index < (cmp_cap + 1); index++) {
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len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
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Pstate_fid, Pstate_power, index,
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pcontrol_blk, plen, onlyBSP);
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pcontrol_blk, plen, onlyBSP, control);
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}
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return len;
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}
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#else
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static uint8_t vid_to_reg(uint32_t vid)
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{
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return (1550 - vid) / 25;
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}
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static uint32_t vid_from_reg(uint8_t val)
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{
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return (val == 0x1f ? 0 : 1550 - val * 25);
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}
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static uint8_t freq_to_fid(uint32_t freq)
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{
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return (freq - 800) / 100;
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}
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/* Return a frequency in MHz, given an input fid */
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static uint32_t fid_to_freq(uint32_t fid)
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{
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return 800 + (fid * 100);
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}
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#define MAXP 7
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struct pstate {
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uint16_t freqMhz; /* in MHz */
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uint16_t voltage; /* in mV */
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uint16_t tdp; /* in W * 10 */
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};
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struct cpuentry {
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uint16_t modelnr; /* numeric model value, unused in code */
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uint8_t brandID; /* CPUID 8000_0001h EBX [11:6] (BrandID) */
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uint32_t cpuid; /* CPUID 8000_0001h EAX [31:0] (CPUID) */
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uint8_t maxFID; /* FID/VID Status MaxFID Field */
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uint8_t startFID; /* FID/VID Status StartFID Field */
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uint16_t pwr:12; /* Thermal Design Power of Max P-State *10 (fixed point) */
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/* Other MAX P state are read from CPU, other P states in following table */
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struct pstate pstates[MAXP];
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};
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struct cpuentry entr[] = {
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/* rev E single core, check OSA152FAA5BK */
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{152, 0xc, 0x20f51, 0x12, 0x12, 926,
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{{2400, 1350, 900}, {2200, 1300, 766},
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{2000, 1250, 651}, {1800, 1200, 522},
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{1000, 1100, 320}}},
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{252, 0x10, 0x20f51, 0x12, 0x12, 926,
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{{2400, 1350, 900}, {2200, 1300, 766},
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{2000, 1250, 651}, {1800, 1200, 522},
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{1000, 1100, 320}}},
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{852, 0x14, 0x20f51, 0x12, 0x12, 926,
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{{2400, 1350, 900}, {2200, 1300, 766},
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{2000, 1250, 651}, {1800, 1200, 522},
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{1000, 1100, 320}}},
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{254, 0x10, 0x20f51, 0x14, 0x14, 926,
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{{2600, 1350, 902}, {2400, 1300, 770},
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{2200, 1250, 657}, {2000, 1200, 559},
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{1800, 1150, 476}, {1000, 1100, 361}}},
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{854, 0x14, 0x20f51, 0x14, 0x14, 926,
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{{2600, 1350, 902}, {2400, 1300, 770},
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{2200, 1250, 657}, {2000, 1200, 559},
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{1800, 1150, 476}, {1000, 1100, 361}}},
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{242, 0x10, 0x20f51, 0x8, 0x8, 853,
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{}},
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{842, 0x10, 0x20f51, 0x8, 0x8, 853,
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{}},
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{244, 0x10, 0x20f51, 0xa, 0xa, 853,
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{{1000, 1100, 378}}},
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{844, 0x14, 0x20f51, 0xa, 0xa, 853,
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{{1000, 1100, 378}}},
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{246, 0x10, 0x20f51, 0xc, 0xc, 853,
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{{1800, 1350, 853},
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{1000, 1100, 378}}},
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{846, 0x14, 0x20f51, 0xc, 0xc, 853,
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{{1800, 1350, 853},
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{1000, 1100, 378}}},
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{242, 0x10, 0x20f51, 0x8, 0x8, 853,
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{}},
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{842, 0x14, 0x20f51, 0x8, 0x8, 853,
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{}},
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{244, 0x10, 0x20f51, 0xa, 0xa, 853,
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{{1000, 1100, 378}}},
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{844, 0x14, 0x20f51, 0xa, 0xa, 853,
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{{1000, 1100, 378}}},
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{246, 0x10, 0x20f51, 0xc, 0xc, 853,
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{{1800, 1350, 827}, {1000, 1100, 366}}},
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{846, 0x14, 0x20f51, 0xc, 0xc, 853,
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{{1800, 1350, 827}, {1000, 1100, 366}}},
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{248, 0x10, 0x20f51, 0xe, 0xe, 853,
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{{2000, 1350, 827}, {1800, 1300, 700},
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{1000, 1100, 366}}},
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{848, 0x14, 0x20f51, 0xe, 0xe, 853,
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{{2000, 1350, 827}, {1800, 1300, 700},
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{1000, 1100, 366}}},
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{250, 0x10, 0x20f51, 0x10, 0x10, 853,
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{{2200, 1350, 853}, {2000, 1300, 827},
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{1800, 1250, 702}, {1000, 1100, 301}}},
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{850, 0x14, 0x20f51, 0x10, 0x10, 853,
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{{2200, 1350, 853}, {2000, 1300, 827},
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{1800, 1250, 702}, {1000, 1100, 301}}},
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/* begin OSK246FAA5BL */
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{246, 0x12, 0x20f51, 0xc, 0xc, 547,
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{{1800, 1350, 461}, {1000, 1100, 223}}},
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{846, 0x16, 0x20f51, 0xc, 0xc, 547,
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{{1800, 1350, 461}, {1000, 1100, 223}}},
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{148, 0xe, 0x20f51, 0xe, 0xe, 547,
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{{2000, 1350, 521}, {1800, 1300, 459},
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{1000, 1100, 211}}},
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{248, 0x12, 0x20f51, 0xe, 0xe, 547,
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{{2000, 1350, 521}, {1800, 1300, 459},
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{1000, 1100, 211}}},
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{848, 0x16, 0x20f51, 0xe, 0xe, 547,
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{{2000, 1350, 521}, {1800, 1300, 459},
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{1000, 1100, 211}}},
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{250, 0x12, 0x20f51, 0x10, 0x10, 547,
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{{2200, 1350, 521}, {2000, 1300, 440},
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{1800, 1250, 379}, {1000, 1100, 199}}},
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{850, 0x16, 0x20f51, 0x10, 0x10, 547,
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{{2200, 1350, 521}, {2000, 1300, 440},
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{1800, 1250, 379}, {1000, 1100, 199}}},
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{144, 0xc, 0x20f71, 0xa, 0xa, 670,
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{{1000, 1100, 296}}},
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{148, 0xc, 0x20f71, 0xe, 0xe, 853,
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{{2000, 1350, 830}, {1800, 1300, 704},
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{1000, 1100, 296}}},
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{152, 0xc, 0x20f71, 0x12, 0x12, 104,
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{{2400, 1350, 1016}, {2200, 1300, 863},
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{2000, 1250, 732}, {1800, 1200, 621},
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{1000, 1100, 419}}},
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{146, 0xc, 0x20f71, 0xc, 0xc, 670,
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{{1800, 1350, 647}, {1000, 1100, 286}}},
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{150, 0xc, 0x20f71, 0x10, 0x10, 853,
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{{2200, 1350, 830}, {2000, 1300, 706},
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{1800, 1250, 596}, {1000, 1100, 350}}},
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{154, 0xc, 0x20f71, 0x14, 0x14, 1040,
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{{2600, 1350, 1017}, {2400, 1300, 868},
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{2200, 1250, 740}, {2000, 1200, 630},
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{1800, 1150, 537}, {1000, 1100, 416}}},
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/* rev E dualcore */
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{165, 0x2c, 0x20f12, 0xa, 0xa, 950,
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{{1000, 1100, 406}}},
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{265, 0x30, 0x20f12, 0xa, 0xa, 950,
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{{1000, 1100, 406}}},
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{865, 0x34, 0x20f12, 0xa, 0xa, 950,
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{{1000, 1100, 406}}},
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{270, 0x30, 0x20f12, 0xc, 0xc, 950,
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{{1800, 1300, 903}, {1000, 1100, 383}}},
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{870, 0x34, 0x20f12, 0xc, 0xc, 950,
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{{1800, 1300, 903}, {1000, 1100, 383}}},
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{275, 0x30, 0x20f12, 0xe, 0xe, 950,
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{{2000, 1300, 903}, {1800, 1250, 759},
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{1000, 1100, 361}}},
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{875, 0x34, 0x20f12, 0xe, 0xe, 950,
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{{2000, 1300, 903}, {1800, 1250, 759},
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{1000, 1100, 361}}},
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{280, 0x30, 0x20f12, 0x10, 0x10, 926,
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{{2400, 1350, 900}, {2200, 1300, 766},
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{1800, 1200, 552}, {1000, 1100, 320}}},
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{880, 0x34, 0x20f12, 0x10, 0x10, 926,
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{{2400, 1350, 900}, {2200, 1300, 766},
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{1800, 1200, 552}, {1000, 1100, 320}}},
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{170, 0x2c, 0x20f32, 0xc, 0xc, 1100,
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{{1800, 1300, 1056}, {1000, 1100, 514}}},
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{175, 0x2c, 0x20f32, 0xe, 0xe, 1100,
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{{2000, 1300, 1056}, {1800, 1250, 891},
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{1000, 1100, 490}}},
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{260, 0x32, 0x20f32, 0x8, 0x8, 550,
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{}},
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{860, 0x36, 0x20f32, 0x8, 0x8, 550,
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{}},
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{165, 0x2e, 0x20f32, 0xa, 0xa, 550,
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{{1000, 1100, 365}}},
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{265, 0x32, 0x20f32, 0xa, 0xa, 550,
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{{1000, 1100, 365}}},
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{865, 0x36, 0x20f32, 0xa, 0xa, 550,
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{{1000, 1100, 365}}},
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{270, 0x32, 0x20f12, 0xc, 0xc, 550,
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{{1800, 1150, 520}, {1000, 1100, 335}}},
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{870, 0x36, 0x20f12, 0xc, 0xc, 550,
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{{1800, 1150, 520}, {1000, 1100, 335}}},
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{180, 0x2c, 0x20f32, 0x10, 0x10, 1100,
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{{2200, 1300, 1056}, {2000, 1250, 891},
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{1800, 1200, 748}, {1000, 1100, 466}}},
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{3000, 0x4, 0x10ff0, 0xa, 0xa, 670,
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{{1000, 1100, 210}}},
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};
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static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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{
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u8 cmp_cap;
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struct cpuentry *data = NULL;
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uint32_t control;
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int i = 0, index, len = 0, Pstate_num = 0;
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msr_t msr;
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u8 Pstate_fid[10];
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u16 Pstate_feq[10];
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u8 Pstate_vid[10];
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u32 Pstate_power[10];
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u8 Max_fid, Start_fid, Start_vid, Max_vid;
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struct cpuid_result cpuid1 = cpuid(0x80000001);
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msr = rdmsr(0xc0010042);
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Max_fid = (msr.lo & 0x3F0000) >> 16;
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Max_vid = (msr.hi & 0x3F0000) >> 16;
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Start_fid = (msr.lo & 0x3F00) >> 8;
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Start_vid = (msr.hi & 0x3F00) >> 8;
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cmp_cap =
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(pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) &
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0x3000) >> 12;
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for (i = 0; i < ARRAY_SIZE(entr); i++) {
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if ((entr[i].cpuid == cpuid1.eax)
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&& (entr[i].startFID == Start_fid)
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&& (entr[i].maxFID == Max_fid)
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&& (entr[i].brandID == ((u8 )((cpuid1.ebx >> 6) & 0xff)))) {
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data = &entr[i];
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break;
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}
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}
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if (data == NULL) {
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printk(BIOS_WARNING, "Unknown CPU, please update the powernow_acpi.c\n");
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return 0;
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}
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/* IRT 80us, PLL_LOCK_TIME 2us, MVS 25mv, VST 100us */
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control = (3 << 30) | (2 << 20) | (0 << 18) | (5 << 11) | (1 << 29);
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len = 0;
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Pstate_num = 0;
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Pstate_fid[Pstate_num] = Max_fid;
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Pstate_feq[Pstate_num] = fid_to_freq(Max_fid);
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Pstate_vid[Pstate_num] = Max_vid;
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Pstate_power[Pstate_num] = data->pwr * 100;
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Pstate_num++;
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do {
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Pstate_fid[Pstate_num] = freq_to_fid(data->pstates[Pstate_num - 1].freqMhz) & 0x3f;
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Pstate_feq[Pstate_num] = data->pstates[Pstate_num - 1].freqMhz;
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Pstate_vid[Pstate_num] = vid_to_reg(data->pstates[Pstate_num - 1].voltage);
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Pstate_power[Pstate_num] = data->pstates[Pstate_num - 1].tdp * 100;
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Pstate_num++;
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} while ((Pstate_num < MAXP) && (data->pstates[Pstate_num].freqMhz != 0));
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for (i=0;i<Pstate_num;i++)
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printk(BIOS_DEBUG, "P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n", i,
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Pstate_feq[i],
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vid_from_reg(Pstate_vid[i]),
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Pstate_power[i]);
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for (index = 0; index < (cmp_cap + 1); index++) {
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len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
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Pstate_fid, Pstate_power, index,
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pcontrol_blk, plen, onlyBSP, control);
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}
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return len;
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}
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#endif
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int amd_model_fxx_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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{
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int lens;
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|
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@ -388,11 +654,3 @@ int amd_model_fxx_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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return lens;
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}
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#else
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int amd_model_fxx_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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{
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return 0;
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}
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#endif
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|
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@ -232,6 +232,12 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
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pmio_write(0x42, byte);
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pmio_write(0x89, 0x10);
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/* Toggle the LDT_STOP# during FID/VID Change, this bit is documented
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only in SB600!
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While here, enable C states too
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*/
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pmio_write(0x67, 0x6);
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}
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void hard_reset(void)
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Reference in New Issue