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Revert "mb/google/brya: Enable south XHCI ports 1 and 2" 

This reverts commit f7f715dff3.

Reason for revert: FSP 2207.01 uses the UsbTcPortEn UPD for TCSS XHCI enable

BUG=b:184324979
TEST=boot brya, all 3 USB Type-C ports still enumerate devices

Change-Id: I82bae21d185247bc0f3580fd6f92abb8eece6732
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56132
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2021-07-15 14:10:00 +00:00
parent ad5307e46c
commit 19a2b84944
1 changed files with 0 additions and 6 deletions
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6
src/mainboard/google/brya/variants/baseboard/devicetree.cb
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@ -46,12 +46,6 @@ chip soc/intel/alderlake
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0
# TODO(b/184324979): Workaround to enable TCSS ports. FSP v2081
# uses port enable for south XHCI ports to determine if TCSS
# ports should be enabled. Until FSP is fixed, enable south
# XHCI ports 1 and 2.
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"