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soc/intel/skylake: Correct SMBUS_SLAVE_ADDR definition 

According to document 332691-003EN (SPT-H datasheet volume 2), the
hardware defaults to 0x44, which matches what newer platforms use.

Change-Id: I494587b0074ab3675c3e88676375f667e757cdf0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50941
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-02-19 20:01:31 +01:00
parent 8a269deee6
commit 19af7bc822
1 changed files with 6 additions and 2 deletions
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8
src/soc/intel/skylake/include/soc/smbus.h
View File

@ -17,7 +17,11 @@
#define TCO_INTRD_SEL_SMI (1 << 2)
#define TCO_INTRD_SEL_INT (1 << 1)
/* SMBus I/O bits. */
#define SMBUS_SLAVE_ADDR 0x24
/*
* Default slave address value for PCH. This value is set to match default
* value set by hardware. It is useful since PCH is able to respond even
* before CPU is up. This is reset by RSMRST# but not by PLTRST#.
*/
#define SMBUS_SLAVE_ADDR 0x44
#endif