soc/amd/stoneyridge: Remove sb_util.c

Obsolete pm_acpi_pm_cnt_blk(), and remove it and pm_acpi_pm_evt_blk().

Relocate the remaining functions to get/save UMA information to
southbridge.c.

Change-Id: I90c4394e3cf26f4ad60a078948a84303bda693d0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32659
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/stoneyridge/Makefile.inc

@@ -46,7 +46,6 @@ bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 bootblock-y += monotonic_timer.c
 bootblock-y += pmutil.c
 bootblock-y += reset.c
-bootblock-y += sb_util.c
 bootblock-y += tsc_freq.c
 bootblock-y += southbridge.c
 bootblock-y += nb_util.c
@@ -61,7 +60,6 @@ romstage-y += gpio.c
 romstage-y += monotonic_timer.c
 romstage-y += pmutil.c
 romstage-y += reset.c
-romstage-y += sb_util.c
 romstage-y += smbus.c
 romstage-y += smbus_spd.c
 romstage-y += ramtop.c
@@ -75,7 +73,6 @@ romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
 verstage-y += gpio.c
 verstage-y += i2c.c
 verstage-y += monotonic_timer.c
-verstage-y += sb_util.c
 verstage-y += pmutil.c
 verstage-y += reset.c
 verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
@@ -86,7 +83,6 @@ verstage-$(CONFIG_SPI_FLASH) += spi.c
 postcar-y += monotonic_timer.c
 postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
 postcar-y += ramtop.c
-postcar-y += sb_util.c
 postcar-y += nb_util.c
 postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c
 postcar-y += tsc_freq.c
@@ -101,7 +97,6 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += gpio.c
 ramstage-y += monotonic_timer.c
 ramstage-y += southbridge.c
-ramstage-y += sb_util.c
 ramstage-y += northbridge.c
 ramstage-y += pmutil.c
 ramstage-y += reset.c
@@ -121,7 +116,6 @@ ramstage-y += nb_util.c
 smm-y += monotonic_timer.c
 smm-y += smihandler.c
 smm-y += smi_util.c
-smm-y += sb_util.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_DEBUG_SMI) += uart.c
 smm-$(CONFIG_SPI_FLASH) += spi.c

src/soc/amd/stoneyridge/include/soc/southbridge.h

@@ -356,8 +356,6 @@ void southbridge_final(void *chip_info);
 void southbridge_init(void *chip_info);
 void sb_read_mode(u32 mode);
 void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
-uint16_t pm_acpi_pm_cnt_blk(void);
-uint16_t pm_acpi_pm_evt_blk(void);
 void bootblock_fch_early_init(void);
 void bootblock_fch_init(void);
 /**

src/soc/amd/stoneyridge/sb_util.c

@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/mmio.h>
-#include <arch/acpi.h>
-#include <amdblocks/acpimmio.h>
-#include <soc/southbridge.h>
-
-uint16_t pm_acpi_pm_cnt_blk(void)
-{
-	return pm_read16(PM1_CNT_BLK);
-}
-
-uint16_t pm_acpi_pm_evt_blk(void)
-{
-	return pm_read16(PM_EVT_BLK);
-}
-
-void save_uma_size(uint32_t size)
-{
-	biosram_write32(BIOSRAM_UMA_SIZE, size);
-}
-
-void save_uma_base(uint64_t base)
-{
-	biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base);
-	biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32));
-}
-
-uint32_t get_uma_size(void)
-{
-	return biosram_read32(BIOSRAM_UMA_SIZE);
-}
-
-uint64_t get_uma_base(void)
-{
-	uint64_t base;
-	base = biosram_read32(BIOSRAM_UMA_BASE);
-	base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32);
-	return base;
-}

src/soc/amd/stoneyridge/smihandler.c

@@ -199,7 +199,7 @@ static void sb_slp_typ_handler(void)
 		 * An IO cycle is required to trigger the STPCLK/STPGNT
 		 * handshake when the Pm1 write is reissued.
 		 */
-		outw(pm1cnt | SLP_EN, pm_acpi_pm_cnt_blk());
+		outw(pm1cnt | SLP_EN, pm_read16(PM1_CNT_BLK));
 		hlt();
 	}
 }

src/soc/amd/stoneyridge/southbridge.c

@@ -649,3 +649,27 @@ static void set_pci_irqs(void *unused)
  * on entry into BS_DEV_ENABLE.
  */
 BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);
+
+void save_uma_size(uint32_t size)
+{
+	biosram_write32(BIOSRAM_UMA_SIZE, size);
+}
+
+void save_uma_base(uint64_t base)
+{
+	biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base);
+	biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32));
+}
+
+uint32_t get_uma_size(void)
+{
+	return biosram_read32(BIOSRAM_UMA_SIZE);
+}
+
+uint64_t get_uma_base(void)
+{
+	uint64_t base;
+	base = biosram_read32(BIOSRAM_UMA_BASE);
+	base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32);
+	return base;
+}