soc/intel/common/pch: Make infrastructure ready for pch common code

This patch is intended to make Intel common PCH code based on
Gen-6 Sunrisepoint PCH (SPT).

All common PCH code blocks between Gen-6 till latest-PCH should be
part of soc/intel/common/pch/ directory.

A SoC Kconfig might select this option to include base PCH package
while building new SOC block. Currently majority of
common IP code blocks are part of soc/intel/common/block/ and
SoC Kconfig just select those Kconfig option. Now addition to that
SoC might only selects required base PCH block to include those
common IP block selections.

BUG=none
BRANCH=b:78109109
TEST=soc code can select PCH config option

Change-Id: I2934e3b1aed9d692eb00df18ce69a7fcd3096f6b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/common/Kconfig

@@ -8,6 +8,9 @@ if SOC_INTEL_COMMON
 comment "Intel SoC Common Code"
 source "src/soc/intel/common/block/Kconfig"
 
+comment "Intel SoC Common PCH Code"
+source "src/soc/intel/common/pch/Kconfig"
+
 config DISPLAY_MTRRS
 	bool "MTRRs: Display the MTRR settings"
 	default n

src/soc/intel/common/Makefile.inc

@@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y)
 
 subdirs-y += basecode/
 subdirs-y += block/
+subdirs-y += pch/
 
 bootblock-y += util.c
 

src/soc/intel/common/pch/Kconfig

@@ -0,0 +1,45 @@
+config SOC_INTEL_COMMON_PCH_BASE
+	bool
+	depends on SOC_INTEL_COMMON_BLOCK
+	help
+	  All common PCH code blocks between Gen-6 till latest-PCH should be
+	  part of this directory. A SoC Kconfig might select this option to include
+	  base PCH package while building new SOC block. Currently majority of
+	  common IP code blocks are part of soc/intel/common/block/ and
+	  SoC Kconfig just select those Kconfig option. Addition to that SoC
+	  code now having option to select required base PCH block to include
+	  common IP block.
+
+if SOC_INTEL_COMMON_PCH_BASE
+
+comment "Intel SoC Common PCH Code"
+source "src/soc/intel/common/pch/*/Kconfig"
+
+config PCH_SPECIFIC_OPTIONS
+	def_bool y
+	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
+	select SOC_INTEL_COMMON_BLOCK_CSE
+	select SOC_INTEL_COMMON_BLOCK_DSP
+	select SOC_INTEL_COMMON_BLOCK_EBDA
+	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
+	select SOC_INTEL_COMMON_BLOCK_GPIO
+	select SOC_INTEL_COMMON_BLOCK_GRAPHICS
+	select SOC_INTEL_COMMON_BLOCK_ITSS
+	select SOC_INTEL_COMMON_BLOCK_I2C
+	select SOC_INTEL_COMMON_BLOCK_LPC
+	select SOC_INTEL_COMMON_BLOCK_LPSS
+	select SOC_INTEL_COMMON_BLOCK_P2SB
+	select SOC_INTEL_COMMON_BLOCK_PCIE
+	select SOC_INTEL_COMMON_BLOCK_PCR
+	select SOC_INTEL_COMMON_BLOCK_PMC
+	select SOC_INTEL_COMMON_BLOCK_RTC
+	select SOC_INTEL_COMMON_BLOCK_SATA
+	select SOC_INTEL_COMMON_BLOCK_SCS
+	select SOC_INTEL_COMMON_BLOCK_SMBUS
+	select SOC_INTEL_COMMON_BLOCK_SPI
+	select SOC_INTEL_COMMON_BLOCK_TIMER
+	select SOC_INTEL_COMMON_BLOCK_UART
+	select SOC_INTEL_COMMON_BLOCK_XDCI
+	select SOC_INTEL_COMMON_BLOCK_XHCI
+
+endif

src/soc/intel/common/pch/Makefile.inc

@@ -0,0 +1,5 @@
+subdirs-$(CONFIG_SOC_INTEL_COMMON_PCH_BASE) += ./*
+
+ifeq ($(CONFIG_SOC_INTEL_COMMON_PCH_BASE),y)
+CPPFLAGS_common += -I$(src)/soc/intel/common/pch/include/
+endif