northbridge/amd/amdfam10: Update DRAM speed limits for C32 sockets
The existing code applied G34-specific speed limits to all socket types. Update G34 and C32 specific speed limits to be in line with BKDG recommendations. Change-Id: I958ad333c47948ae741a56de5866af3e636fd24d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13140 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Timothy Pearson
Martin Roth
parent
a39e6d1cf9
commit
19ce16ae69
1 changed files with 265 additions and 93 deletions
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@ -180,68 +180,243 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8
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}
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if (is_fam15h()) {
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if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
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/* Fam15h BKDG Rev. 3.14 Table 27 */
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if (voltage & 0x4) {
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/* 1.25V */
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if (count > 1) {
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if (highest_rank_count > 1) {
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/* Limit to DDR3-1066 */
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if (freq > 533) {
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freq = 533;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage));
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if (CONFIG_CPU_SOCKET_TYPE == 0x15) {
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/* Socket G34 */
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if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
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/* Fam15h BKDG Rev. 3.14 Table 27 */
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if (voltage & 0x4) {
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/* 1.25V */
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if (count > 1) {
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if (highest_rank_count > 1) {
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/* Limit to DDR3-1066 */
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if (freq > 533) {
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freq = 533;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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} else if (voltage & 0x2) {
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/* 1.35V */
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if (count > 1) {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1600 */
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if (freq > 800) {
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freq = 800;
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printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else if (voltage & 0x1) {
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/* 1.50V */
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if (count > 1) {
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/* Limit to DDR3-1600 */
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if (freq > 800) {
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freq = 800;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1866 */
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if (freq > 933) {
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freq = 933;
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printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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}
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} else if (voltage & 0x2) {
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/* 1.35V */
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if (count > 1) {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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} else {
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/* Fam15h BKDG Rev. 3.14 Table 26 */
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if (voltage & 0x4) {
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/* 1.25V */
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if (count > 1) {
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if (highest_rank_count > 1) {
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/* Limit to DDR3-1066 */
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if (freq > 533) {
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freq = 533;
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printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else {
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/* Limit to DDR3-1600 */
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if (freq > 800) {
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freq = 800;
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printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
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} else if (voltage & 0x2) {
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/* 1.35V */
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if (MaxDimmsInstallable > 1) {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1600 */
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if (freq > 800) {
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freq = 800;
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printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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}
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} else if (voltage & 0x1) {
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/* 1.50V */
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if (count > 1) {
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/* Limit to DDR3-1600 */
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if (freq > 800) {
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freq = 800;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1866 */
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if (freq > 933) {
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freq = 933;
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printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage));
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} else if (voltage & 0x1) {
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if (MaxDimmsInstallable == 1) {
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if (count > 1) {
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/* Limit to DDR3-1600 */
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if (freq > 800) {
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freq = 800;
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printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1866 */
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if (freq > 933) {
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freq = 933;
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printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else {
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if (count > 1) {
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if (highest_rank_count > 1) {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1600 */
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if (freq > 800) {
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freq = 800;
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printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else {
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/* Limit to DDR3-1600 */
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if (freq > 800) {
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freq = 800;
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printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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}
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}
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}
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} else {
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/* Fam15h BKDG Rev. 3.14 Table 26 */
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if (voltage & 0x4) {
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/* 1.25V */
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if (count > 1) {
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if (highest_rank_count > 1) {
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} else if (CONFIG_CPU_SOCKET_TYPE == 0x14) {
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/* Socket C32 */
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if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
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/* Fam15h BKDG Rev. 3.14 Table 30 */
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if (voltage & 0x4) {
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/* 1.25V */
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if (count > 1) {
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if (highest_rank_count > 2) {
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/* Limit to DDR3-800 */
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if (freq > 400) {
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freq = 400;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else if (voltage & 0x2) {
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/* 1.35V */
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if (count > 1) {
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if (highest_rank_count > 2) {
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/* Limit to DDR3-800 */
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if (freq > 400) {
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freq = 400;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage));
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}
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} else if (highest_rank_count > 1) {
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/* Limit to DDR3-1066 */
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if (freq > 533) {
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freq = 533;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else {
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/* Limit to DDR3-1600 */
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if (freq > 800) {
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freq = 800;
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printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else if (voltage & 0x1) {
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/* 1.50V */
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if (count > 1) {
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if (highest_rank_count > 2) {
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/* Limit to DDR3-800 */
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if (freq > 400) {
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freq = 400;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage));
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}
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} else if (highest_rank_count > 1) {
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/* Limit to DDR3-1066 */
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if (freq > 533) {
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freq = 533;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else {
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if (highest_rank_count > 2) {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1600 */
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if (freq > 800) {
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freq = 800;
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printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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}
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}
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} else {
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/* Fam15h BKDG Rev. 3.14 Table 29 */
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if (voltage & 0x4) {
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/* 1.25V */
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if (count > 1) {
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/* Limit to DDR3-1066 */
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if (freq > 533) {
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freq = 533;
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@ -251,70 +426,67 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else if (voltage & 0x2) {
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/* 1.35V */
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if (MaxDimmsInstallable > 1) {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1600 */
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if (freq > 800) {
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freq = 800;
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printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else if (voltage & 0x1) {
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if (MaxDimmsInstallable == 1) {
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if (count > 1) {
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/* Limit to DDR3-1600 */
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if (freq > 800) {
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freq = 800;
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printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1866 */
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if (freq > 933) {
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freq = 933;
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printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else {
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} else if (voltage & 0x2) {
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if (count > 1) {
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if (highest_rank_count > 1) {
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/* Limit to DDR3-1066 */
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if (freq > 533) {
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freq = 533;
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printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1600 */
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if (freq > 800) {
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freq = 800;
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printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else if (voltage & 0x1) {
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if (MaxDimmsInstallable == 1) {
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/* Limit to DDR3-1600 */
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if (freq > 800) {
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freq = 800;
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printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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if (count > 1) {
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if (highest_rank_count > 1) {
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/* Limit to DDR3-1066 */
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if (freq > 533) {
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freq = 533;
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printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage));
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}
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} else {
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/* Limit to DDR3-1333 */
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if (freq > 666) {
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freq = 666;
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printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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} else {
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/* Limit to DDR3-1600 */
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if (freq > 800) {
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freq = 800;
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printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
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}
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}
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}
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}
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||||
}
|
||||
} else {
|
||||
/* TODO
|
||||
* Other socket support unimplemented
|
||||
*/
|
||||
}
|
||||
} else {
|
||||
if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
|
||||
|
|
|
|||
Loading…
Reference in a new issue