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northbridge/amd/amdfam10: Update DRAM speed limits for C32 sockets

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The existing code applied G34-specific speed limits to all socket
types.  Update G34 and C32 specific speed limits to be in line with
BKDG recommendations.

Change-Id: I958ad333c47948ae741a56de5866af3e636fd24d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13140
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Timothy Pearson 2015-11-24 14:11:47 -06:00 committed by Martin Roth
parent a39e6d1cf9
commit 19ce16ae69
1 changed files with 265 additions and 93 deletions
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358
src/northbridge/amd/amdfam10/raminit_amdmct.c
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@ -180,68 +180,243 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8
} }
if (is_fam15h()) { if (is_fam15h()) {
if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { if (CONFIG_CPU_SOCKET_TYPE == 0x15) {
/* Fam15h BKDG Rev. 3.14 Table 27 */ /* Socket G34 */
if (voltage & 0x4) { if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
/* 1.25V */ /* Fam15h BKDG Rev. 3.14 Table 27 */
if (count > 1) { if (voltage & 0x4) {
if (highest_rank_count > 1) { /* 1.25V */
/* Limit to DDR3-1066 */ if (count > 1) {
if (freq > 533) { if (highest_rank_count > 1) {
freq = 533; /* Limit to DDR3-1066 */
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); if (freq > 533) {
freq = 533;
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage));
}
} else {
/* Limit to DDR3-1333 */
if (freq > 666) {
freq = 666;
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
}
} }
} else { } else {
/* Limit to DDR3-1333 */ /* Limit to DDR3-1333 */
if (freq > 666) { if (freq > 666) {
freq = 666; freq = 666;
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
} }
} }
} else { } else if (voltage & 0x2) {
/* Limit to DDR3-1333 */ /* 1.35V */
if (freq > 666) { if (count > 1) {
freq = 666; /* Limit to DDR3-1333 */
printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); if (freq > 666) {
freq = 666;
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
}
} else {
/* Limit to DDR3-1600 */
if (freq > 800) {
freq = 800;
printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
}
}
} else if (voltage & 0x1) {
/* 1.50V */
if (count > 1) {
/* Limit to DDR3-1600 */
if (freq > 800) {
freq = 800;
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
}
} else {
/* Limit to DDR3-1866 */
if (freq > 933) {
freq = 933;
printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage));
}
} }
} }
} else if (voltage & 0x2) { } else {
/* 1.35V */ /* Fam15h BKDG Rev. 3.14 Table 26 */
if (count > 1) { if (voltage & 0x4) {
/* Limit to DDR3-1333 */ /* 1.25V */
if (freq > 666) { if (count > 1) {
freq = 666; if (highest_rank_count > 1) {
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); /* Limit to DDR3-1066 */
if (freq > 533) {
freq = 533;
printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage));
}
} else {
/* Limit to DDR3-1333 */
if (freq > 666) {
freq = 666;
printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
}
}
} else {
/* Limit to DDR3-1333 */
if (freq > 666) {
freq = 666;
printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
}
} }
} else { } else if (voltage & 0x2) {
/* Limit to DDR3-1600 */ /* 1.35V */
if (freq > 800) { if (MaxDimmsInstallable > 1) {
freq = 800; /* Limit to DDR3-1333 */
printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); if (freq > 666) {
freq = 666;
printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
}
} else {
/* Limit to DDR3-1600 */
if (freq > 800) {
freq = 800;
printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
}
} }
} } else if (voltage & 0x1) {
} else if (voltage & 0x1) { if (MaxDimmsInstallable == 1) {
/* 1.50V */ if (count > 1) {
if (count > 1) { /* Limit to DDR3-1600 */
/* Limit to DDR3-1600 */ if (freq > 800) {
if (freq > 800) { freq = 800;
freq = 800; printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); }
} } else {
} else { /* Limit to DDR3-1866 */
/* Limit to DDR3-1866 */ if (freq > 933) {
if (freq > 933) { freq = 933;
freq = 933; printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage));
printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage)); }
}
} else {
if (count > 1) {
if (highest_rank_count > 1) {
/* Limit to DDR3-1333 */
if (freq > 666) {
freq = 666;
printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
}
} else {
/* Limit to DDR3-1600 */
if (freq > 800) {
freq = 800;
printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
}
}
} else {
/* Limit to DDR3-1600 */
if (freq > 800) {
freq = 800;
printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
}
}
} }
} }
} }
} else { } else if (CONFIG_CPU_SOCKET_TYPE == 0x14) {
/* Fam15h BKDG Rev. 3.14 Table 26 */ /* Socket C32 */
if (voltage & 0x4) { if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
/* 1.25V */ /* Fam15h BKDG Rev. 3.14 Table 30 */
if (count > 1) { if (voltage & 0x4) {
if (highest_rank_count > 1) { /* 1.25V */
if (count > 1) {
if (highest_rank_count > 2) {
/* Limit to DDR3-800 */
if (freq > 400) {
freq = 400;
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage));
}
} else {
/* Limit to DDR3-1333 */
if (freq > 666) {
freq = 666;
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
}
}
} else {
/* Limit to DDR3-1333 */
if (freq > 666) {
freq = 666;
printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
}
}
} else if (voltage & 0x2) {
/* 1.35V */
if (count > 1) {
if (highest_rank_count > 2) {
/* Limit to DDR3-800 */
if (freq > 400) {
freq = 400;
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage));
}
} else if (highest_rank_count > 1) {
/* Limit to DDR3-1066 */
if (freq > 533) {
freq = 533;
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage));
}
} else {
/* Limit to DDR3-1333 */
if (freq > 666) {
freq = 666;
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
}
}
} else {
/* Limit to DDR3-1600 */
if (freq > 800) {
freq = 800;
printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
}
}
} else if (voltage & 0x1) {
/* 1.50V */
if (count > 1) {
if (highest_rank_count > 2) {
/* Limit to DDR3-800 */
if (freq > 400) {
freq = 400;
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage));
}
} else if (highest_rank_count > 1) {
/* Limit to DDR3-1066 */
if (freq > 533) {
freq = 533;
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage));
}
} else {
/* Limit to DDR3-1333 */
if (freq > 666) {
freq = 666;
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
}
}
} else {
if (highest_rank_count > 2) {
/* Limit to DDR3-1333 */
if (freq > 666) {
freq = 666;
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
}
} else {
/* Limit to DDR3-1600 */
if (freq > 800) {
freq = 800;
printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
}
}
}
}
} else {
/* Fam15h BKDG Rev. 3.14 Table 29 */
if (voltage & 0x4) {
/* 1.25V */
if (count > 1) {
/* Limit to DDR3-1066 */ /* Limit to DDR3-1066 */
if (freq > 533) { if (freq > 533) {
freq = 533; freq = 533;
@ -251,70 +426,67 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8
/* Limit to DDR3-1333 */ /* Limit to DDR3-1333 */
if (freq > 666) { if (freq > 666) {
freq = 666; freq = 666;
printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
} }
} }
} else { } else if (voltage & 0x2) {
/* Limit to DDR3-1333 */
if (freq > 666) {
freq = 666;
printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
}
}
} else if (voltage & 0x2) {
/* 1.35V */
if (MaxDimmsInstallable > 1) {
/* Limit to DDR3-1333 */
if (freq > 666) {
freq = 666;
printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
}
} else {
/* Limit to DDR3-1600 */
if (freq > 800) {
freq = 800;
printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
}
}
} else if (voltage & 0x1) {
if (MaxDimmsInstallable == 1) {
if (count > 1) {
/* Limit to DDR3-1600 */
if (freq > 800) {
freq = 800;
printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
}
} else {
/* Limit to DDR3-1866 */
if (freq > 933) {
freq = 933;
printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage));
}
}
} else {
if (count > 1) { if (count > 1) {
if (highest_rank_count > 1) { if (highest_rank_count > 1) {
/* Limit to DDR3-1066 */
if (freq > 533) {
freq = 533;
printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage));
}
} else {
/* Limit to DDR3-1333 */ /* Limit to DDR3-1333 */
if (freq > 666) { if (freq > 666) {
freq = 666; freq = 666;
printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
} }
} else {
/* Limit to DDR3-1600 */
if (freq > 800) {
freq = 800;
printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
}
} }
} else { } else {
/* Limit to DDR3-1333 */
if (freq > 666) {
freq = 666;
printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
}
}
} else if (voltage & 0x1) {
if (MaxDimmsInstallable == 1) {
/* Limit to DDR3-1600 */ /* Limit to DDR3-1600 */
if (freq > 800) { if (freq > 800) {
freq = 800; freq = 800;
printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
} }
} else {
if (count > 1) {
if (highest_rank_count > 1) {
/* Limit to DDR3-1066 */
if (freq > 533) {
freq = 533;
printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage));
}
} else {
/* Limit to DDR3-1333 */
if (freq > 666) {
freq = 666;
printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage));
}
}
} else {
/* Limit to DDR3-1600 */
if (freq > 800) {
freq = 800;
printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage));
}
}
} }
} }
} }
} else {
/* TODO
* Other socket support unimplemented
*/
} }
} else { } else {
if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {