google/caroline: Add as a variant of glados
Add google/caroline (Samsung Chromebook Pro) as a variant of
glados Skylake reference board:
- add caroline-specific DPTF, EC config, GPIO config, Kconfig,
NHLT config, PEI data, VBT, SPD data, and devicetree
- add caroline-specific memory-init param to romstage
- adjust mainboard EC SCI events for boards with tablet function
Adapted from Chromium branch firmware-glados-7820.B, commit
b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX]
Test: build/boot google/caroline, verify correct functionality
Change-Id: I611a4e76581ba2e5b42e1bc48b0a5b8c70f3598e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Matt DeVillier
Martin Roth
parent
57dd073369
commit
19e7060d7f
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@ -36,6 +36,7 @@ config MAINBOARD_DIR
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config MAINBOARD_PART_NUMBER
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string
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default "Caroline" if BOARD_GOOGLE_CAROLINE
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default "Chell" if BOARD_GOOGLE_CHELL
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default "Glados" if BOARD_GOOGLE_GLADOS
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default "Lars" if BOARD_GOOGLE_LARS
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@ -47,6 +48,7 @@ config MAINBOARD_FAMILY
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config VARIANT_DIR
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string
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default "caroline" if BOARD_GOOGLE_CAROLINE
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default "chell" if BOARD_GOOGLE_CHELL
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default "glados" if BOARD_GOOGLE_GLADOS
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default "lars" if BOARD_GOOGLE_LARS
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@ -54,6 +56,7 @@ config VARIANT_DIR
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config DEVICETREE
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string
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default "variants/caroline/devicetree.cb" if BOARD_GOOGLE_CAROLINE
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default "variants/chell/devicetree.cb" if BOARD_GOOGLE_CHELL
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default "variants/glados/devicetree.cb" if BOARD_GOOGLE_GLADOS
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default "variants/lars/devicetree.cb" if BOARD_GOOGLE_LARS
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@ -87,6 +90,7 @@ config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
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config GBB_HWID
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string
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depends on CHROMEOS
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default "CAROLINE TEST 0958" if BOARD_GOOGLE_CAROLINE
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default "CHELL TEST 6297" if BOARD_GOOGLE_CHELL
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default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS
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default "LARS TEST 5001" if BOARD_GOOGLE_LARS
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@ -1,5 +1,14 @@
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comment "Glados"
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config BOARD_GOOGLE_CAROLINE
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bool "-> Caroline (Samsung Chromebook Pro)"
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select BOARD_GOOGLE_BASEBOARD_GLADOS
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select DRIVERS_INTEL_WIFI
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select DSAR_ENABLE
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select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS
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select SAR_ENABLE
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select USE_SAR
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config BOARD_GOOGLE_CHELL
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bool "-> Chell (HP Chromebook 13 G1)"
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select BOARD_GOOGLE_BASEBOARD_GLADOS
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@ -19,7 +19,26 @@
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#include <ec/ec.h>
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#include <ec/google/chromeec/ec_commands.h>
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#include <variant/ec.h>
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#ifdef EC_ENABLE_TABLET_EVENT
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#define MAINBOARD_EC_SCI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
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#else
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#define MAINBOARD_EC_SCI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
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@ -35,6 +54,7 @@
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
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#endif
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#define MAINBOARD_EC_SMI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
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@ -71,4 +71,6 @@ void mainboard_memory_init_params(struct romstage_params *params,
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sizeof(params->pei_data->RcompTarget));
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memory_params->MemorySpdDataLen = SPD_LEN;
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memory_params->DqPinsInterleaved = FALSE;
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if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CAROLINE))
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memory_params->DdrFreqLimit = 1600;
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}
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@ -0,0 +1,16 @@
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91 20 F1 03 05 1A 05 0A 03 11 01 08 08 00 50 15
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78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
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00 00 C2 08 00 00 00 A8 00 88 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00
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4B 34 45 42 45 33 30 34 45 42 2D 45 47 43 47 20
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20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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@ -0,0 +1,40 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2016 Google Inc.
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## Copyright (C) 2016 Intel Corporation
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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romstage-y += variant.c
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ramstage-y += variant.c
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smm-y += variant.c
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SPD_BIN = $(obj)/spd.bin
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# SPD data by index
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SPD_SOURCES = samsung_dimm_K4E8E324EB-EGCF # 0b0000
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SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0001
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SPD_SOURCES += samsung_dimm_K4EBE304EB-EGCG # 0b0010
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SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
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# Include spd ROM data
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$(SPD_BIN): $(SPD_DEPS)
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for f in $+; \
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do for c in $$(cat $$f | grep -v ^#); \
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do printf $$(printf '\%o' 0x$$c); \
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done; \
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done > $@
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cbfs-files-y += spd.bin
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spd.bin-file := $(SPD_BIN)
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spd.bin-type := spd
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@ -0,0 +1,6 @@
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Vendor name: Google
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Board name: Caroline (Samsung Chromebook Pro)
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Category: laptop
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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Binary file not shown.
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@ -0,0 +1,268 @@
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chip soc/intel/skylake
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# Enable deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "1"
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register "deep_s5_enable_dc" = "1"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_B"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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# Enable DPTF
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register "dptf_enable" = "1"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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register "EnableLan" = "0"
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register "EnableSata" = "0"
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register "SataSalpSupport" = "0"
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register "SataMode" = "0"
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register "SataPortsEnable[0]" = "0"
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register "EnableAzalia" = "1"
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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register "ScsEmmcEnabled" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsSdCardEnabled" = "2"
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register "PttSwitch" = "0"
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register "InternalGfx" = "1"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "1"
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register "HeciEnabled" = "0"
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register "SaGv" = "3"
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register "SerialIrqConfigSirqEnable" = "1"
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register "PmConfigSlpS3MinAssert" = "2" # 50ms
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register "PmConfigSlpS4MinAssert" = "1" # 1s
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register "PmConfigSlpSusMinAssert" = "1" # 500ms
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmTimerDisabled" = "1"
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# TCC offset
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register "tcc_offset" = "10"
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# VR Slew rate setting for improving audible noise
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register "AcousticNoiseMitigation" = "1"
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register "SlowSlewRateForIa" = "3" # Fast/16
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register "SlowSlewRateForGt" = "3" # Fast/16
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register "SlowSlewRateForSa" = "0" # Fast/2
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register "FastPkgCRampDisable" = "0"
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# VR Settings Configuration for 5 Domains
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#+----------------+-------+-------+-------------+-------------+-------+
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#| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
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#+----------------+-------+-------+-------------+-------------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-------+-------+-------------+-------------+-------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(4),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(4),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(24),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_RING]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(24),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(24),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(24),
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.voltage_limit = 1520,
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}"
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# Enable Root port 1.
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register "PcieRpEnable[0]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[0]" = "1"
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# RP 1 uses SRCCLKREQ1#
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register "PcieRpClkReqNumber[0]" = "1"
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port (main)
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register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (sub)
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Empty
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register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
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register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (main)
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (sub)
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register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty
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register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
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# Must leave UART0 enabled or SD/eMMC will not work as PCI
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
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[PchSerialIoIndexSpi0] = PchSerialIoDisabled,
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[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
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[PchSerialIoIndexUart0] = PchSerialIoPci,
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[PchSerialIoIndexUart1] = PchSerialIoDisabled,
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
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}"
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# I2C4 is 1.8V
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register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
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# PL2 override 15W
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register "tdp_pl2_override" = "15"
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 15.0 on
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chip drivers/i2c/generic
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register "hid" = ""ATML0001""
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register "desc" = ""Atmel Touchscreen""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
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device i2c 4b on end
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end
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end # I2C #0
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device pci 15.1 on
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chip drivers/i2c/generic
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register "hid" = ""ATML0000""
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register "desc" = ""Atmel Touchpad""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
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register "wake" = "GPE0_DW0_05"
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device i2c 4a on end
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end
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end # I2C #1
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device pci 15.2 on end # I2C #2
|
||||
device pci 15.3 off end # I2C #3
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 17.0 off end # SATA
|
||||
device pci 19.0 on end # UART #2
|
||||
device pci 19.1 off end # I2C #5
|
||||
device pci 19.2 on end # I2C #4
|
||||
device pci 1c.0 on
|
||||
chip drivers/intel/wifi
|
||||
register "wake" = "GPE0_DW0_16"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
end # PCI Express Port 1
|
||||
device pci 1c.1 off end # PCI Express Port 2
|
||||
device pci 1c.2 off end # PCI Express Port 3
|
||||
device pci 1c.3 off end # PCI Express Port 4
|
||||
device pci 1c.4 off end # PCI Express Port 5
|
||||
device pci 1c.5 off end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 off end # PCI Express Port 9
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1e.0 on end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1e.4 on end # eMMC
|
||||
device pci 1e.5 off end # SDIO
|
||||
device pci 1e.6 on end # SDCard
|
||||
device pci 1f.0 on
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
chip ec/google/chromeec
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end # LPC Interface
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2016 Google Inc.
|
||||
* Copyright (C) 2016 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define DPTF_CPU_PASSIVE 80
|
||||
#define DPTF_CPU_CRITICAL 100
|
||||
|
||||
#define DPTF_TSR0_SENSOR_ID 1
|
||||
#define DPTF_TSR0_SENSOR_NAME "Ambient"
|
||||
#define DPTF_TSR0_PASSIVE 48
|
||||
#define DPTF_TSR0_CRITICAL 90
|
||||
#define DPTF_TSR0_TABLET_PASSIVE 44
|
||||
#define DPTF_TSR0_TABLET_CRITICAL 90
|
||||
|
||||
#define DPTF_TSR1_SENSOR_ID 2
|
||||
#define DPTF_TSR1_SENSOR_NAME "Charger"
|
||||
#define DPTF_TSR1_PASSIVE 48
|
||||
#define DPTF_TSR1_CRITICAL 90
|
||||
#define DPTF_TSR1_TABLET_PASSIVE 44
|
||||
#define DPTF_TSR1_TABLET_CRITICAL 90
|
||||
|
||||
#define DPTF_TSR2_SENSOR_ID 3
|
||||
#define DPTF_TSR2_SENSOR_NAME "DRAM"
|
||||
#define DPTF_TSR2_PASSIVE 48
|
||||
#define DPTF_TSR2_CRITICAL 90
|
||||
#define DPTF_TSR2_TABLET_PASSIVE 44
|
||||
#define DPTF_TSR2_TABLET_CRITICAL 90
|
||||
|
||||
#define DPTF_TSR3_SENSOR_ID 4
|
||||
#define DPTF_TSR3_SENSOR_NAME "WiFi"
|
||||
#define DPTF_TSR3_PASSIVE 48
|
||||
#define DPTF_TSR3_CRITICAL 90
|
||||
#define DPTF_TSR3_TABLET_PASSIVE 44
|
||||
#define DPTF_TSR3_TABLET_CRITICAL 90
|
||||
|
||||
/* SKL-Y is Fanless design */
|
||||
#undef DPTF_ENABLE_FAN_CONTROL
|
||||
|
||||
/* Enable DPTF charger control */
|
||||
#define DPTF_ENABLE_CHARGER
|
||||
|
||||
/* Charger performance states, board-specific values from charger and EC */
|
||||
Name (CHPS, Package () {
|
||||
Package () { 0, 0, 0, 0, 255, 0xbb8, "mA", 0 }, /* 3000mA (MAX) */
|
||||
Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1500mA */
|
||||
Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1000mA */
|
||||
Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 500mA */
|
||||
Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 500mA */
|
||||
})
|
||||
|
||||
Name (DTRT, Package () {
|
||||
/* CPU Throttle Effect on CPU */
|
||||
Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 0 */
|
||||
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 1 */
|
||||
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 2 */
|
||||
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 90, 0, 0, 0, 0 },
|
||||
|
||||
/* Charger Effect on Temp Sensor 2 */
|
||||
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 600, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 3 */
|
||||
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
|
||||
})
|
||||
|
||||
Name (MPPC, Package ()
|
||||
{
|
||||
0x2, /* Revision */
|
||||
Package () { /* Power Limit 1 */
|
||||
0, /* PowerLimitIndex, 0 for Power Limit 1 */
|
||||
3000, /* PowerLimitMinimum */
|
||||
7000, /* PowerLimitMaximum */
|
||||
5000, /* TimeWindowMinimum */
|
||||
5000, /* TimeWindowMaximum */
|
||||
200 /* StepSize */
|
||||
},
|
||||
Package () { /* Power Limit 2 */
|
||||
1, /* PowerLimitIndex, 1 for Power Limit 2 */
|
||||
15000, /* PowerLimitMinimum */
|
||||
15000, /* PowerLimitMaximum */
|
||||
1000, /* TimeWindowMinimum */
|
||||
1000, /* TimeWindowMaximum */
|
||||
1000 /* StepSize */
|
||||
}
|
||||
})
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <variant/gpio.h>
|
||||
|
||||
#define BOARD_DIG_I2C_ADDR 0x09
|
||||
#define BOARD_DIG_IRQ DIG_INT_L
|
||||
#define BOARD_DIG_PDCT DIG_PDCT_L
|
||||
#define BOARD_DIG_EJECT GPE_DIG_EJECT
|
||||
|
||||
Scope (\_SB)
|
||||
{
|
||||
Device (PENH)
|
||||
{
|
||||
Name (_HID, "PRP0001")
|
||||
|
||||
Name (_CRS, ResourceTemplate () {
|
||||
GpioIo (Exclusive, PullNone, 0, 0, IoRestrictionInputOnly,
|
||||
"\\_SB.PCI0.GPIO", 0, ResourceConsumer) { GPIO_DIG_EJECT }
|
||||
})
|
||||
|
||||
Name (_DSD, Package () {
|
||||
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package () {
|
||||
Package () {
|
||||
"compatible",
|
||||
Package () { "gpio-keys"}
|
||||
},
|
||||
}
|
||||
})
|
||||
|
||||
Device (EJCT)
|
||||
{
|
||||
Name (_ADR, Zero)
|
||||
|
||||
Name (_DSD, Package () {
|
||||
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package () {
|
||||
/* SW_PEN_INSERTED */
|
||||
Package () { "linux,code", 0xf },
|
||||
/* EV_SW type */
|
||||
Package () { "linux,input-type", 0x5 },
|
||||
Package () { "label", "pen_eject" },
|
||||
Package () { "gpios",
|
||||
Package () {
|
||||
^^PENH, 0, 0, 1 /* inserted active low */
|
||||
}
|
||||
},
|
||||
}
|
||||
})
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_SB.PCI0.I2C2)
|
||||
{
|
||||
Name (FMCN, Package () { 87, 197, 26 })
|
||||
|
||||
Device (DIGI)
|
||||
{
|
||||
Name (_HID, "ACPI0C50")
|
||||
Name (_CID, "PNP0C50")
|
||||
Name (_UID, 1)
|
||||
Name (_S0W, 4)
|
||||
Name (_PRW, Package () { BOARD_DIG_EJECT, 3 })
|
||||
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
I2cSerialBus (
|
||||
BOARD_DIG_I2C_ADDR,
|
||||
ControllerInitiated,
|
||||
400000,
|
||||
AddressingMode7Bit,
|
||||
"\\_SB.PCI0.I2C2",
|
||||
)
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow)
|
||||
{
|
||||
BOARD_DIG_IRQ
|
||||
}
|
||||
})
|
||||
|
||||
/*
|
||||
* Function 1 returns the offset in the I2C device register
|
||||
* address space at which the HID descriptor can be read.
|
||||
*
|
||||
* Arg0 = UUID
|
||||
* Arg1 = revision number of requested function
|
||||
* Arg2 = requested function number
|
||||
* Arg3 = function specific parameter
|
||||
*/
|
||||
Method (_DSM, 4, NotSerialized)
|
||||
{
|
||||
If (LEqual (Arg0, ToUUID
|
||||
("3cdff6f7-4267-4555-ad05-b30a3d8938de"))) {
|
||||
If (LEqual (Arg2, Zero)) {
|
||||
/* Function 0 - Query */
|
||||
If (LEqual (Arg1, One)) {
|
||||
/* Revision 1 Function 1 */
|
||||
Return (Buffer (One) { 0x03 })
|
||||
} Else {
|
||||
/* Revision 2+ not supported */
|
||||
Return (Buffer (One) { 0x00 })
|
||||
}
|
||||
} ElseIf (LEqual (Arg2, One)) {
|
||||
/* Function 1 - HID Descriptor Addr */
|
||||
Return (0x0001)
|
||||
} Else {
|
||||
/* Function 2+ not supported */
|
||||
Return (Buffer (One) { 0x00 })
|
||||
}
|
||||
} Else {
|
||||
Return (Buffer (One) { 0x00 })
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* EC ENABLE TABLET EVENT */
|
||||
#define EC_ENABLE_TABLET_EVENT
|
||||
|
|
@ -0,0 +1,254 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* EC in RW */
|
||||
#define GPIO_EC_IN_RW GPP_C6
|
||||
|
||||
/* BIOS Flash Write Protect */
|
||||
#define GPIO_PCH_WP GPP_C23
|
||||
|
||||
/* Memory configuration board straps */
|
||||
#define GPIO_MEM_CONFIG_0 GPP_C12
|
||||
#define GPIO_MEM_CONFIG_1 GPP_C13
|
||||
#define GPIO_MEM_CONFIG_2 GPP_C14
|
||||
#define GPIO_MEM_CONFIG_3 GPP_C15
|
||||
|
||||
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
|
||||
#define GPE_EC_WAKE GPE0_LAN_WAK
|
||||
|
||||
/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
|
||||
#define GPE_WLAN_WAKE GPE0_DW0_16
|
||||
|
||||
/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */
|
||||
#define GPE_TOUCHPAD_WAKE GPE0_DW0_05
|
||||
|
||||
/* GPP_B15 is DIG_EJECT. GPP_B group is routed to DW0 in the GPE0 block */
|
||||
#define GPE_DIG_EJECT GPE0_DW0_15
|
||||
/* Notification DIG_EJECT */
|
||||
#define GPIO_DIG_EJECT GPP_B19
|
||||
|
||||
/* Input device interrupt configuration */
|
||||
#define TOUCHPAD_INT_L GPP_B3_IRQ
|
||||
#define TOUCHSCREEN_INT_L GPP_E7_IRQ
|
||||
#define MIC_INT_L GPP_F10_IRQ
|
||||
#define DIG_INT_L GPP_F11_IRQ
|
||||
#define DIG_PDCT_L GPP_F7_IRQ
|
||||
|
||||
/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
|
||||
#define EC_SCI_GPI GPE0_DW2_16
|
||||
#define EC_SMI_GPI GPP_E15
|
||||
|
||||
/* Power rail control signals. */
|
||||
#define EN_PP3300_DX_DIG GPP_C11
|
||||
#define EN_PP3300_DX_TOUCH GPP_C22
|
||||
#define EN_PP3300_DX_EMMC GPP_D5
|
||||
#define EN_PP1800_DX_EMMC GPP_D6
|
||||
#define EN_PP3300_DX_CAM GPP_D12
|
||||
|
||||
/* SD controller needs additional card detect GPIO to support RTD3 */
|
||||
#define GPIO_SD_CARD_DETECT GPP_A7
|
||||
|
||||
#ifndef __ACPI__
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
|
||||
/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
|
||||
/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
|
||||
/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
|
||||
/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
/* PIRQA# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), /* SD_CD_INT_L */
|
||||
/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
|
||||
/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10),
|
||||
/* PME# */ PAD_CFG_NC(GPP_A11),
|
||||
/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
|
||||
/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
|
||||
/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
|
||||
/* ISH_GP0 */ PAD_CFG_NC(GPP_A18),
|
||||
/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
|
||||
/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),
|
||||
/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
|
||||
/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
|
||||
/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
|
||||
/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),
|
||||
/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
|
||||
/* VRALERT# */ PAD_CFG_NC(GPP_B2),
|
||||
/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TOUCHPAD */
|
||||
/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),
|
||||
/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */
|
||||
/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */
|
||||
/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7),
|
||||
/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8),
|
||||
/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9),
|
||||
/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),
|
||||
/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11),
|
||||
/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
/* SPKR */ PAD_CFG_NC(GPP_B14),
|
||||
/* GSPI0_CS# */ PAD_CFG_GPI_ACPI_SCI(GPP_B15, NONE, DEEP, NONE), /* DIG EJECT */
|
||||
/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */
|
||||
/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17),
|
||||
/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18),
|
||||
/* GSPI1_CS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B19, NONE, DEEP), /* non-wake DIG EJECT */
|
||||
/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),
|
||||
/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),
|
||||
/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22),
|
||||
/* SM1ALERT# */ PAD_CFG_NC(GPP_B23),
|
||||
/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */
|
||||
/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */
|
||||
/* SMBALERT# */ PAD_CFG_NC(GPP_C2),
|
||||
/* SML0CLK */ PAD_CFG_NC(GPP_C3),
|
||||
/* SML0DATA */ PAD_CFG_NC(GPP_C4),
|
||||
/* SML0ALERT# */ PAD_CFG_NC(GPP_C5),
|
||||
/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
|
||||
/* SM1DATA */ PAD_CFG_NC(GPP_C7),
|
||||
/* UART0_RXD */ PAD_CFG_NC(GPP_C8),
|
||||
/* UART0_TXD */ PAD_CFG_NC(GPP_C9),
|
||||
/* UART0_RTS# */ PAD_CFG_NC(GPP_C10),
|
||||
/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_DX_DIG */
|
||||
/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
|
||||
/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
|
||||
/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
|
||||
/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */
|
||||
/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */
|
||||
/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */
|
||||
/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TOUCHPAD */
|
||||
/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TOUCHPAD */
|
||||
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
|
||||
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
|
||||
/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */
|
||||
/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
|
||||
/* SPI1_CS# */ PAD_CFG_NC(GPP_D0),
|
||||
/* SPI1_CLK */ PAD_CFG_NC(GPP_D1),
|
||||
/* SPI1_MISO */ PAD_CFG_NC(GPP_D2),
|
||||
/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3),
|
||||
/* FASHTRIG */ PAD_CFG_NC(GPP_D4),
|
||||
/* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */
|
||||
/* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */
|
||||
/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
|
||||
/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
|
||||
/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9),
|
||||
/* ISH_SPI_CLK */ PAD_CFG_NC(GPP_D10),
|
||||
/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11),
|
||||
/* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */
|
||||
/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
|
||||
/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
|
||||
/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),
|
||||
/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),
|
||||
/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17),
|
||||
/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18),
|
||||
/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
/* TS_SPI1_IO2 */ PAD_CFG_NC(GPP_D21),
|
||||
/* TS_SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */
|
||||
/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
|
||||
/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */
|
||||
/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
|
||||
/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2),
|
||||
/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
|
||||
/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4),
|
||||
/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),
|
||||
/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),
|
||||
/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */
|
||||
/* SATALED# */ PAD_CFG_NC(GPP_E8),
|
||||
/* USB2_OCO# */ PAD_CFG_NC(GPP_E9),
|
||||
/* USB2_OC1# */ PAD_CFG_NC(GPP_E10),
|
||||
/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
|
||||
/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
|
||||
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */
|
||||
/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */
|
||||
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18),
|
||||
/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19),
|
||||
/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20),
|
||||
/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21),
|
||||
/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),
|
||||
/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23),
|
||||
/*
|
||||
* The next 4 pads are for bit banging the amplifiers. They are connected
|
||||
* together with i2s0 signals. For default behavior of i2s make these
|
||||
* gpio inupts.
|
||||
*/
|
||||
/* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
|
||||
/* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
|
||||
/* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),
|
||||
/* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),
|
||||
/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* DIG */
|
||||
/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* DIG */
|
||||
/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
|
||||
/* I2C3_SCL */ PAD_CFG_GPI_APIC(GPP_F7, NONE, PLTRST), /* DIG_PDCT_L */
|
||||
/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */
|
||||
/* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */
|
||||
/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */
|
||||
/* I2C5_SCL */ PAD_CFG_GPI_APIC(GPP_F11, NONE, PLTRST), /* DIG_IRQ_L */
|
||||
/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
||||
/* RSVD */ PAD_CFG_NC(GPP_F23),
|
||||
/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
|
||||
/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
|
||||
/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
|
||||
/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
|
||||
/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
|
||||
/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
|
||||
/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
|
||||
/*
|
||||
* SD write protect is not connected but is still sampled, so enable
|
||||
* native function and enable internal pull-down to disable.
|
||||
*/
|
||||
/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),
|
||||
/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||
/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */
|
||||
/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
|
||||
/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
/* RSVD */ PAD_CFG_NC(GPD7),
|
||||
/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* SLP_WLAN# */ PAD_CFG_NC(GPD9),
|
||||
/* SLP_S5# */ PAD_CFG_NC(GPD10),
|
||||
/* LANPHYC */ PAD_CFG_NC(GPD11),
|
||||
};
|
||||
|
||||
/* Early pad configuration in romstage. */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2016 Google Inc.
|
||||
* Copyright (C) 2016 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/variant.h>
|
||||
#include <gpio.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <soc/pei_data.h>
|
||||
#include <soc/pei_wrapper.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
void mainboard_fill_pei_data(struct pei_data *pei_data)
|
||||
{
|
||||
/* DQ byte map */
|
||||
const u8 dq_map[2][12] = {
|
||||
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
|
||||
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
|
||||
{ 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
|
||||
0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
|
||||
/* DQS CPU<>DRAM map */
|
||||
const u8 dqs_map[2][8] = {
|
||||
{ 0, 1, 3, 2, 4, 5, 6, 7 },
|
||||
{ 1, 0, 4, 5, 2, 3, 6, 7 } };
|
||||
|
||||
/* Rcomp resistor */
|
||||
const u16 RcompResistor[3] = { 200, 81, 162 };
|
||||
|
||||
/* Rcomp target */
|
||||
const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
|
||||
|
||||
memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
|
||||
memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
|
||||
memcpy(pei_data->RcompResistor, RcompResistor,
|
||||
sizeof(RcompResistor));
|
||||
memcpy(pei_data->RcompTarget, RcompTarget,
|
||||
sizeof(RcompTarget));
|
||||
}
|
||||
|
||||
void mainboard_gpio_smi_sleep(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Power down the rails on any sleep type. */
|
||||
gpio_t active_high_signals[] = {
|
||||
EN_PP3300_DX_DIG,
|
||||
EN_PP3300_DX_TOUCH,
|
||||
EN_PP3300_DX_EMMC,
|
||||
EN_PP1800_DX_EMMC,
|
||||
EN_PP3300_DX_CAM,
|
||||
};
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(active_high_signals); i++)
|
||||
gpio_set(active_high_signals[i], 0);
|
||||
}
|
||||
Loading…
Reference in New Issue