cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup
Pineview CPUs support a non-eviction mode that ought to be used during cache as ram setup. This assumes that all atoms that need to set a special register to enable L2 cache are socketed and hence uses a static Kconfig option to set that MSR on affected CPUs. Tested on Foxconn D41S, still boots. Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30863 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -36,3 +36,4 @@ source src/cpu/intel/fit/Kconfig
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source src/cpu/intel/turbo/Kconfig
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source src/cpu/intel/common/Kconfig
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source src/cpu/intel/microcode/Kconfig
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source src/cpu/intel/car/non-evict/Kconfig
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@ -0,0 +1,5 @@
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config CPU_HAS_L2_ENABLE_MSR
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bool
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help
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Select this in Kconfig of CPU sockets/SOC where the CPU
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has an MSR to enable the L2 CPU cache
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@ -24,6 +24,7 @@
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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#define NoEvictMod_MSR 0x2e0
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#define BBL_CR_CTL3_MSR 0x11e
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.global bootblock_pre_c_entry
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@ -133,6 +134,18 @@ addrsize_set_high:
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orl $MTRR_DEF_TYPE_EN, %eax
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wrmsr
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#if IS_ENABLED(CONFIG_CPU_HAS_L2_ENABLE_MSR)
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/*
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* Enable the L2 cache. Currently this assumes that this
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* only affect socketed CPU's for which this is always valid,
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* hence the static preprocesser.
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*/
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movl $BBL_CR_CTL3_MSR, %ecx
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rdmsr
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orl $0x100, %eax
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wrmsr
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#endif
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/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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@ -1,5 +1,7 @@
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config CPU_INTEL_SOCKET_FCBGA559
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bool
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help
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Select this socket on Intel Pineview
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if CPU_INTEL_SOCKET_FCBGA559
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@ -8,6 +10,7 @@ config SOCKET_SPECIFIC_OPTIONS
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select CPU_INTEL_MODEL_106CX
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select MMX
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select SSE
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select CPU_HAS_L2_ENABLE_MSR
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config DCACHE_RAM_BASE
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hex
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@ -8,7 +8,7 @@ subdirs-y += ../microcode
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subdirs-y += ../hyperthreading
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subdirs-y += ../speedstep
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cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
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postcar-y += ../car/p4-netburst/exit_car.S
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cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
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postcar-y += ../car/non-evict/exit_car.S
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romstage-y += ../car/romstage.c
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