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soc/mediatek/mt8183: fine tune the phy timing 

To fix MIPI D-PHY test failure, the hs-prepare should be less than
LimitMin from spec, and we have to enlarge TEOT margin.

BUG=b:138344447
BRANCH=kukui
TEST=Boots correctly on kukui

Change-Id: If91e7a546866299f02432be27fe778be5d7bdc5f
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Jitao Shi 2019-10-21 16:47:18 +08:00 committed by Patrick Georgi
parent 68ff7298ec
commit 19e961e83c
1 changed files with 2 additions and 2 deletions
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4
src/soc/mediatek/common/dsi.c
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@ -81,9 +81,9 @@ static void mtk_dsi_phy_timing(int data_rate, struct mtk_phy_timing *phy_timing)
memset(phy_timing, 0, sizeof(*phy_timing)); memset(phy_timing, 0, sizeof(*phy_timing));
phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); phy_timing->lpx = DIV_ROUND_UP(60, cycle_time);
phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time); phy_timing->da_hs_prepare = DIV_ROUND_UP((50 + 5 * ui), cycle_time);
phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time); phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time);
phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time); phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 77), cycle_time);
phy_timing->ta_go = 4U * phy_timing->lpx; phy_timing->ta_go = 4U * phy_timing->lpx;
phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; phy_timing->ta_sure = 3U * phy_timing->lpx / 2U;